AT89C51RE2-SLSUM Atmel, AT89C51RE2-SLSUM Datasheet - Page 146

• Manufacturer Part Number: AT89C51RE2-SLSUM
• Description: MCU 8BIT FLASH 2.7-5.5V 44-PLCC
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C51RE2-SLSUM

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 60MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Package: 44PLCC
• Device Core: 8051
• Family Name: 89C
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 34
• Interface Type: SPI/TWI/UART
• Number Of Timers: 3
• Processor Series: AT89x
• Core: 8051
• Data Ram Size: 8 KB
• Maximum Clock Frequency: 40 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: AT89OCD-01
• Minimum Operating Temperature: - 40 C
• Cpu Family: 89C
• Device Core Size: 8b
• Frequency (max): 40MHz
• Total Internal Ram Size: 8KB
• # I/os (max): 34
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: PLCC
• For Use With: AT89OCD-01 - USB EMULATOR FOR AT8XC51 MCUAT89STK-11 - KIT STARTER FOR AT89C51RX2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Registers
146
AT89C51RE2
Table 107. SSCON Register
SSCON - Synchronous Serial Control register (93h)
Table 108. SSDAT (95h) - Syncrhonous Serial Data register (read/write)
Number
Number
CR2
SD7
Bit
Bit
7
7
6
5
4
3
2
1
0
7
7
6
5
4
3
2
Mnemonic Description
Mnemonic Description
SSIE
SSIE
CR2
CR1
CR0
SD6
SD7
SD6
SD5
SD4
SD3
SD2
STA
ST0
Bit
Bit
AA
SI
6
6
Control Rate bit 2
See Table 101.
Synchronous Serial Interface Enable bit
Clear to disable the TWI module.
Set to enable the TWI module.
Start flag
Set to send a START condition on the bus.
Stop flag
Set to send a STOP condition on the bus.
Synchronous Serial Interrupt flag
Set by hardware when a serial interrupt is requested.
Must be cleared by software to acknowledge interrupt.
Assert Acknowledge flag
Clear in master and slave receiver modes, to force a not acknowledge (high level
on SDA).
Clear to disable SLA or GCA recognition.
Set to recognise SLA or GCA (if GC set) for entering slave receiver or transmitter
modes.
Set in master and slave receiver modes, to force an acknowledge (low level on
SDA).
This bit has no effect when in master transmitter mode.
Control Rate bit 1
See Table 101.
Control Rate bit 0
See Table 101.
Address bit 7 or Data bit 7.
Address bit 6 or Data bit 6.
Address bit 5 or Data bit 5.
Address bit 4 or Data bit 4.
Address bit 3 or Data bit 3.
Address bit 2 or Data bit 2.
STA
SD5
5
5
STO
SD4
4
4
SD3
SI
3
3
SD2
AA
2
2
CR1
SD1
1
1
7663D–8051–10/08
CR0
SD0
0
0