PIC18F2450-I/SO Microchip Technology, PIC18F2450-I/SO Datasheet - Page 208

• Manufacturer Part Number: PIC18F2450-I/SO
• Description: IC PIC MCU FLASH 8KX16 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2450-I/SO

• Program Memory Type: FLASH
• Program Memory Size: 16KB (8K x 16)
• Package / Case: 28-SOIC (7.5mm Width)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: UART/USART, USB
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 23
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: EUSART/USB
• Maximum Clock Frequency: 48 MHZ
• Number Of Programmable I/os: 23
• Number Of Timers: 3
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163014, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Package: 28SOIC W
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 48 MHz
• A/d Bit Size: 10 bit
• A/d Channels Available: 10
• Height: 2.31 mm
• Length: 17.87 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2 V
• Width: 7.49 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164322 - MODULE SOCKET MPLAB PM3 28/44QFNDM163025 - PIC DEM FULL SPEED USB DEMO BRD
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

microcontroller to continue operation in the event of an
PIC18F2450/4450
18.4
The Fail-Safe Clock Monitor (FSCM) allows the
external oscillator failure by automatically switching the
device clock to the internal oscillator. The FSCM function
is enabled by setting the FCMEN Configuration bit.
When FSCM is enabled, the INTRC oscillator runs at all
times to monitor clocks to peripherals and provide a
backup clock in the event of a clock failure. Clock
monitoring (shown in Figure 18-3) is accomplished by
creating a sample clock signal, which is the INTRC output
divided by 64. This allows ample time between FSCM
sample clocks for a peripheral clock edge to occur. The
peripheral device clock and the sample clock are
presented as inputs to the Clock Monitor latch (CM). The
CM is set on the falling edge of the device clock source,
but cleared on the rising edge of the sample clock.
FIGURE 18-3:
Clock failure is tested for on the falling edge of the
sample clock. If a sample clock falling edge occurs
while CM is still set, a clock failure has been detected
(Figure 18-4). This causes the following:
• the FSCM generates an oscillator fail interrupt by
• the device clock source is switched to the internal
• the WDT is reset.
DS39760C-page 206
setting bit, OSCFIF (PIR2<7>);
oscillator (OSCCON is not updated to show the cur-
rent clock source – this is the fail-safe condition); and
Peripheral
Source
(32 μs)
INTRC
Clock
Fail-Safe Clock Monitor
(2.048 ms)
488 Hz
÷ 64
FSCM BLOCK DIAGRAM
(edge-triggered)
Clock Monitor
Latch (CM)
C
S
Q
Q
Detected
Failure
Clock
Preliminary
The FSCM will detect failures of the primary or
secondary clock sources only. If the internal oscillator
fails, no failure would be detected, nor would any action
be possible.
18.4.1
Both the FSCM and the WDT are clocked by the
INTRC oscillator. Since the WDT operates with a
separate divider and counter, disabling the WDT has
no effect on the operation of the INTRC oscillator when
the FSCM is enabled.
If the WDT is enabled with a small prescale value, a
decrease in clock speed allows a WDT time-out to
occur and a subsequent device Reset. For this reason,
Fail-Safe Clock Monitor events also reset the WDT and
postscaler, allowing it to start timing from when execu-
tion speed was changed and decreasing the likelihood
of an erroneous time-out.
18.4.2
The fail-safe condition is terminated by either a device
Reset or by entering a power-managed mode. On
Reset, the controller starts the primary clock source
specified in Configuration Register 1H (with any start-
up delays that are required for the oscillator mode,
such as OST or PLL timer). The INTRC provides the
device clock until the primary clock source becomes
ready (similar to a Two-Speed Start-up). The clock
source is then switched to the primary clock (indicated
by the OSTS bit in the OSCCON register becoming
set). The Fail-Safe Clock Monitor then resumes
monitoring the peripheral clock.
The primary clock source may never become ready
during start-up. In this case, operation is clocked by the
INTRC. The OSCCON register will remain in its Reset
state until a power-managed mode is entered.
FSCM AND THE WATCHDOG TIMER
EXITING FAIL-SAFE OPERATION
© 2007 Microchip Technology Inc.