C8051F320DK Silicon Laboratories Inc, C8051F320DK Datasheet - Page 99

• Manufacturer Part Number: C8051F320DK
• Description: DEV KIT FOR C8051F320/F321
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F320DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F320/F321
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F320
• Silicon Family Name: C8051F32x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: Silicon Laboratories C8051F320, C8051F321
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1260

10. Reset Sources
Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this
reset state, the following occur:
•
•
•
•
All SFRs are reset to the predefined values noted in the SFR detailed descriptions. The contents of internal
data memory are unaffected during a reset; any previously stored data is preserved. However, since the
stack pointer SFR is reset, the stack is effectively lost even though the data on the stack is not altered.
The Port I/O latches are reset to 0xFF (all logic ones) in open-drain mode. Weak pull-ups are enabled dur-
ing and after the reset. For VDD Monitor and Power-On Resets, the /RST pin is driven low until the device
exits the reset state.
On exit from the reset state, the program counter (PC) is reset, and the system clock defaults to the inter-
nal oscillator. Refer to Section “13. Oscillators” on page 116 for information on selecting and configuring
the system clock source. The Watchdog Timer is enabled with the system clock divided by 12 as its clock
source (Section “20.3. Watchdog Timer Mode” on page 236 details the use of the Watchdog Timer). Pro-
gram execution begins at location 0x0000.
XTAL1
XTAL2
CIP-51 halts program execution
Special Function Registers (SFRs) are initialized to their defined reset values
External Port pins are forced to a known state
Interrupts and timers are disabled.
Oscillator
Oscillator
Multiplier
External
Internal
Clock
Drive
Px.x
Px.x
System
Clock
Clock Select
Comparator 0
Figure 10.1. Reset Sources
+
-
Detector
Missing
Clock
(one-
shot)
Microcontroller
EN
Extended Interrupt
C0RSEF
CIP-51
Core
Handler
VDD
WDT
PCA
EN
Rev. 1.4
Supply
Monitor
+
-
System Reset
Enable
Software Reset (SWRSF)
Power On
Reset
Operation
FLASH
Errant
Controller
'0'
USB
C8051F320/1
(wired-OR)
Transition
VBUS
Reset
Funnel
/RST
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