C8051F320DK Silicon Laboratories Inc, C8051F320DK Datasheet - Page 219

• Manufacturer Part Number: C8051F320DK
• Description: DEV KIT FOR C8051F320/F321
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F320DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F320/F321
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F320
• Silicon Family Name: C8051F32x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: Silicon Laboratories C8051F320, C8051F321
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1260

19.2.3. USB Start-of-Frame Capture
When T2SOF = ‘1’, Timer 2 operates in USB Start-of-Frame (SOF) capture mode. When T2SPLIT = ‘0’,
Timer 2 counts up and overflows from 0xFFFF to 0x0000. Each time a USB SOF is received, the contents
of
(TMR2RLH:TMR2RLL). A Timer 2 interrupt is generated if enabled. This mode can be used to calibrate the
system clock or external oscillator against the known USB host SOF clock.
When T2SPLIT = ‘1’, the Timer 2 registers (TMR2H and TMR2L) act as two 8-bit counters. Each counter
counts up independently and overflows from 0xFF to 0x00. Each time a USB SOF is received, the contents
of the Timer 2 registers are latched into the Timer 2 Reload registers (TMR2RLH and TMR2RLL). A
Timer 2 interrupt is generated if enabled.
the
External Clock / 8
Timer 2
SYSCLK / 12
External Clock / 8
T
F
2
H
T
F
2
L
SYSCLK / 12
TMR2CN
Figure 19.6. Timer 2 SOF Capture Mode (T2SPLIT = ‘0’)
Figure 19.7. Timer 2 SOF Capture Mode (T2SPLIT = ‘1’)
T
F
2
L
E
N
O
T
2
S
F
registers
SYSCLK
T
2
S
P
L
T
I
H
R
T
F
2
T
2
T
F
2
L
TMR2CN
C
T
F
2
L
E
N
T
2
X
L
K
0
1
T
S
O
F
2
S
P
T
2
L
T
I
R
T
2
SYSCLK
(TMR2H:TMR2L)
T
2
X
C
L
K
0
1
M
H
T
3
M
T
3
L
Start-of-Frame
CKCON
M
T
2
H
0
1
1
0
T
M
0
1
2
L
M
H
T
3
(SOF)
USB
M
T
1
M
T
3
L
M
CKCON
T
0
M
H
T
2
S
C
A
1
M
T
2
L
S
C
A
0
M
T
1
M
T
0
TR2
TR2
S
C
A
1
S
C
A
0
Rev. 1.4
are
Enable
Capture
TCLK
TCLK
TCLK
latched
Overflow
TMR2RLH
TMR2RLL
TL2
TMR2H
TMR2L
TMR2RLL TMR2RLH
TMR2L
Interrupt
into
Capture
Capture
To SMBus
TMR2H
To SMBus
To ADC,
SMBus
the
Timer 2
C8051F320/1
Start-of-Frame
Enable
(SOF)
USB
To ADC,
SMBus
Reload
Interrupt
registers
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