C8051F320DK Silicon Laboratories Inc, C8051F320DK Datasheet - Page 22

DEV KIT FOR C8051F320/F321

C8051F320DK

Manufacturer Part Number
C8051F320DK
Description
DEV KIT FOR C8051F320/F321
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheets

Specifications of C8051F320DK

Contents
Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
Processor To Be Evaluated
C8051F320/F321
Interface Type
USB
Silicon Manufacturer
Silicon Labs
Core Architecture
8051
Silicon Core Number
C8051F320
Silicon Family Name
C8051F32x
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
Silicon Laboratories C8051F320, C8051F321
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1260

Available stocks

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Manufacturer
Quantity
Price
Part Number:
C8051F320DK
Manufacturer:
SiliconL
Quantity:
4
C8051F320/1
be socketed. Silicon Labs' debug paradigm increases ease of use and preserves the performance of the
precision analog peripherals.
1.6.
C8051F320 devices include 25 I/O pins (three byte-wide Ports and one 1-bit-wide Port); C8051F321
devices include 21 I/O pins (two byte-wide Ports, one 4-bit-wide Port, and one 1-bit-wide Port). The
C8051F320/1 Ports behave like typical 8051 Ports with a few enhancements. Each Port pin may be config-
ured as an analog input or a digital I/O pin. Pins selected as digital I/Os may additionally be configured for
push-pull or open-drain output. The “weak pull-ups” that are fixed on typical 8051 devices may be globally
disabled, providing power savings capabilities.
The Digital Crossbar allows mapping of internal digital system resources to Port I/O pins (See Figure 1.7).
On-chip counter/timers, serial buses, HW interrupts, comparator outputs, and other digital signals in the
controller can be configured to appear on the Port I/O pins specified in the Crossbar Control registers. This
allows the user to select the exact mix of general purpose Port I/O and digital resources needed for the
particular application.
22
Programmable Digital I/O and Crossbar
PC
Figure 1.6. Development/In-System Debug Diagram
Cable
USB
USB Debug Adapter
Rev. 1.4
Adapter
AC/DC
SILICON LABORATORIES
P1.6
Port 2
Port 1
PWR
Target Board
Port 0
Port 3
MCU
Port 4

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