C8051F320DK Silicon Laboratories Inc, C8051F320DK Datasheet - Page 57

• Manufacturer Part Number: C8051F320DK
• Description: DEV KIT FOR C8051F320/F321
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F320DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F320/F321
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F320
• Silicon Family Name: C8051F32x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: Silicon Laboratories C8051F320, C8051F321
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1260

7.
C8051F320/1 devices include two on-chip programmable voltage Comparators: Comparator0 is shown in
Figure 7.1; Comparator1 is shown in Figure 7.2. The two Comparators operate identically with the follow-
ing exceptions: (1) Their input selections differ as shown in Figure 7.1 and Figure 7.2; (2) Comparator0 can
be used as a reset source.
Each Comparator offers programmable response time and hysteresis, an analog input multiplexer, and two
outputs that are optionally available at the Port pins: a synchronous “latched” output (CP0, CP1), or an
asynchronous “raw” output (CP0A, CP1A). The asynchronous signal is available even when the system
clock is not active. This allows the Comparators to operate and generate an output with the device in
STOP mode. When assigned to a Port pin, the Comparator outputs may be configured as open drain or
push-pull (see Section “14.2. Port I/O Initialization” on page 130). Comparator0 may also be used as a
reset source (see Section “10.5. Comparator0 Reset” on page 102).
The Comparator0 inputs are selected in the CPT0MX register (Figure 7.2). The CMX0P1–CMX0P0 bits
select the Comparator0 positive input; the CMX0N1–CMX0N0 bits select the Comparator0 negative input.
The Comparator1 inputs are selected in the CPT1MX register (Figure 7.5). The CMX1P1–CMX1P0 bits
select the Comparator1 positive input; the CMX1N1–CMX1N0 bits select the Comparator1 negative input.
Important Note About Comparator Inputs: The Port pins selected as Comparator inputs should be con-
figured as analog inputs in their associated Port configuration register, and configured to be skipped by the
Crossbar (for details on Port configuration, see Section “14.3. General Purpose Port I/O” on page 132).
Comparators
CMX0N1
CMX0N0
CMX0P1
CMX0P0
Note: P2.4 and P2.5 available
only on C8051F320
P1.0
P1.4
P2.0
P2.4
P1.1
P1.5
P2.1
P2.5
Figure 7.1. Comparator0 Functional Block Diagram
CP0HYP1
CP0HYP0
CP0HYN1
CP0HYN0
CP0OUT
CP0RIF
CP0FIF
CP0EN
CP0 +
CP0 -
CP0MD1
CP0MD0
CP0RIE
CP0FIE
Rev. 1.4
+
-
VDD
GND
Decision
Reset
Tree
(SYNCHRONIZER)
D
SET
CLR
Q
Q
D
SET
CLR
Q
Q
Rising-edge
CP0
C8051F320/1
Crossbar
Interrupt
Logic
Falling-edge
Interrupt
CP0
CP0A
CP0
CP0
CP0RIE
CP0FIE
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