C8051F320DK Silicon Laboratories Inc, C8051F320DK Datasheet - Page 224

• Manufacturer Part Number: C8051F320DK
• Description: DEV KIT FOR C8051F320/F321
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F320DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F320/F321
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F320
• Silicon Family Name: C8051F32x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: Silicon Laboratories C8051F320, C8051F321
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1260

C8051F320/1
19.3.3. USB Start-of-Frame Capture
When T3SOF = ‘1’, Timer 3 operates in USB Start-of-Frame (SOF) capture mode. When T3SPLIT = ‘0’,
Timer 3 counts up and overflows from 0xFFFF to 0x0000. Each time a USB SOF is received, the contents
of the Timer 3 registers (TMR3H:TMR3L) are latched into the Timer 3 Reload registers
(TMR3RLH:TMR3RLL). A Timer 3 interrupt is generated if enabled. This mode can be used to calibrate the
system clock or external oscillator against the known USB host SOF clock.
When T3SPLIT = ‘1’, the Timer 3 registers (TMR3H and TMR3L) act as two 8-bit counters. Each counter
counts up independently and overflows from 0xFF to 0x00. Each time a USB SOF is received, the contents
of the Timer 3 registers are latched into the Timer 3 Reload registers (TMR3RLH and TMR3RLL). A
Timer 3 interrupt is generated if enabled.
224
External Clock / 8
SYSCLK / 12
External Clock / 8
T
F
3
H
T
F
3
L
TMR3CN
Figure 19.10. Timer 3 SOF Capture Mode (T3SPLIT = ‘0’)
Figure 19.11. Timer 3 SOF Capture Mode (T3SPLIT = ‘1’)
E
N
T
F
3
L
SYSCLK / 12
O
T
3
S
F
SYSCLK
T
3
S
P
L
T
I
T
R
3
H
T
F
3
T
F
3
L
X
C
K
T
3
L
0
1
TMR3CN
N
T
F
3
L
E
O
T
3
S
F
T
S
P
T
3
L
I
T
R
SYSCLK
3
C
T
3
X
L
K
0
1
Start-of-Frame
M
H
T
3
0
1
1
0
M
T
3
L
0
1
(SOF)
USB
CKCON
M
T
2
H
M
H
T
3
M
T
2
L
M
T
3
L
M
T
1
CKCON
M
T
2
H
M
T
0
M
T
2
L
C
TR3
S
A
1
TR3
M
T
1
S
C
A
0
M
T
0
Rev. 1.4
S
C
A
1
S
C
A
0
Enable
TCLK
TCLK
Capture
TCLK
TMR3RLH
TMR3RLL
TMR3H
TMR3L
TMR3RLL TMR3RLH
TMR3L
Interrupt
Capture
Capture
TMR3H
To ADC
Start-of-Frame
(SOF)
Enable
USB
To ADC
Interrupt