STEVAL-IFS003V1 STMicroelectronics, STEVAL-IFS003V1 Datasheet - Page 88

• Manufacturer Part Number: STEVAL-IFS003V1
• Description: BOARD STLM75/STDS75/ST72F651
• Manufacturer: STMicroelectronics

Specifications of STEVAL-IFS003V1

• Design Resources: STEVAL-IFS003V1 Gerber Files STEVAL-IFS003V1 Schematic STEVAL-IFS003V1 Bill of Materials
• Sensor Type: Temperature
• Sensing Range: -55°C ~ 125°C
• Interface: I²C
• Voltage - Supply: 7.5 V ~ 19 V
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: ST72F651, STDS75, STLM75
• Silicon Manufacturer: ST Micro
• Silicon Core Number: STLM75/STDS75 And ST72F651AR6
• Kit Application Type: Sensing - Temperature
• Application Sub Type: Temperature Sensor
• Kit Contents: Board
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Sensitivity: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 497-6238

ST72651AR6
11.5 PWM/BRM GENERATOR (DAC)
11.5.1 Introduction
This PWM/BRM peripheral includes a 6-bit Pulse
Width Modulator (PWM) and a 4-bit Binary Rate
Multiplier (BRM) Generator. It allows the digital to
analog conversion (DAC) when used with external
filtering.
Note: The number of PWM and BRM channels
available depends on the device. Refer to the de-
vice pin description and register map.
11.5.2 Main Features
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■
■
11.5.3 Functional Description
The 10 bits of the 10-bit PWM/BRM are distributed
as 6 PWM bits and 4 BRM bits. The generator con-
sists of a 10-bit counter (common for all channels),
a comparator and the PWM/BRM generation logic.
Figure 48. PWM Generation
88/161
Fixed frequency: f
Resolution: T
Steps of V
PWM OUTPUT
COUNTER
COMPARE
VALUE
DD
000
/2
63
CPU
10
(5mV if V
CPU
OVERFLOW
/64
DD
=5V)
T
CPU
x 64
Doc ID 7215 Rev 4
PWM Generation
The counter increments continuously, clocked at
internal CPU clock. Whenever the 6 least signifi-
cant bits of the counter (defined as the PWM coun-
ter) overflow, the output level for all active chan-
nels is set.
The state of the PWM counter is continuously
compared to the PWM binary weight for each
channel, as defined in the relevant PWM register,
and when a match occurs the output level for that
channel is reset.
This Pulse Width modulated signal must be fil-
tered, using an external RC network placed as
close as possible to the associated pin. This pro-
vides an analog voltage proportional to the aver-
age charge passed to the external capacitor. Thus
for a higher mark/space ratio (high time much
greater than low time) the average output voltage
is higher. The external components of the RC net-
work should be selected for the filtering level re-
quired for control of the system variable.
Each output may individually have its polarity in-
verted by software, and can also be used as a log-
ical output.
OVERFLOW
OVERFLOW
t
t