STEVAL-IFS003V1 STMicroelectronics, STEVAL-IFS003V1 Datasheet - Page 110

• Manufacturer Part Number: STEVAL-IFS003V1
• Description: BOARD STLM75/STDS75/ST72F651
• Manufacturer: STMicroelectronics

Specifications of STEVAL-IFS003V1

• Design Resources: STEVAL-IFS003V1 Gerber Files STEVAL-IFS003V1 Schematic STEVAL-IFS003V1 Bill of Materials
• Sensor Type: Temperature
• Sensing Range: -55°C ~ 125°C
• Interface: I²C
• Voltage - Supply: 7.5 V ~ 19 V
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: ST72F651, STDS75, STLM75
• Silicon Manufacturer: ST Micro
• Silicon Core Number: STLM75/STDS75 And ST72F651AR6
• Kit Application Type: Sensing - Temperature
• Application Sub Type: Temperature Sensor
• Kit Contents: Board
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Sensitivity: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 497-6238

ST72651AR6
I²C SINGLE MASTER BUS INTERFACE (Cont’d)
11.7.7 Register Description
I
Read / Write
Reset Value: 0000 0000 (00h)
Bit 7:6 = Reserved. Forced to 0 by hardware.
Bit 5 = PE Peripheral enable.
This bit is set and cleared by software.
0: Peripheral disabled
1: Master capability
Notes:
– When PE=0, all the bits of the CR register and
– When PE=1, the corresponding I/O pins are se-
– To enable the I
Bit 4 = Reserved. Forced to 0 by hardware.
Bit 3 = START Generation of a Start condition.
This bit is set and cleared by software. It is also
cleared by hardware when the interface is disa-
bled (PE=0) or when the Start condition is sent
(with interrupt generation if ITE=1).
110/161
2
C CONTROL REGISTER (CR)
the SR register except the Stop bit are reset. All
outputs are released while PE=0
lected by hardware as alternate functions.
TWICE with PE=1 as the first write only activates
the interface (only PE is set).
7
0
0
PE
2
C interface, write the CR register
0
START ACK
STOP
Doc ID 7215 Rev 4
ITE
0
– In master mode:
– In idle mode:
Bit 2 = ACK Acknowledge enable.
This bit is set and cleared by software. It is also
cleared by hardware when the interface is disa-
bled (PE=0).
0: No acknowledge returned
1: Acknowledge returned after a data byte is re-
Bit 1 = STOP Generation of a Stop condition.
This bit is set and cleared by software.
Note: This bit is not cleared when the interface is
disabled (PE=0).
– In Master mode only:
Bit 0 = ITE Interrupt enable.
This bit is set and cleared by software and cleared
by hardware when the interface is disabled
(PE=0).
0: Interrupts disabled
1: Interrupts enabled
Refer to
events and the interrupt.
SCL is held low when the SB or BTF flags or an
EV2 event (See
0: No start generation
1: Repeated start generation
0: No start generation
1: Start generation when the bus is free
0: No stop generation
1: Stop generation after the current byte transfer
or after the current Start condition is sent.
ceived
Figure 65
Figure
for the relationship between the
64) is detected.