STEVAL-IFS003V1 STMicroelectronics, STEVAL-IFS003V1 Datasheet - Page 38

• Manufacturer Part Number: STEVAL-IFS003V1
• Description: BOARD STLM75/STDS75/ST72F651
• Manufacturer: STMicroelectronics

Specifications of STEVAL-IFS003V1

• Design Resources: STEVAL-IFS003V1 Gerber Files STEVAL-IFS003V1 Schematic STEVAL-IFS003V1 Bill of Materials
• Sensor Type: Temperature
• Sensing Range: -55°C ~ 125°C
• Interface: I²C
• Voltage - Supply: 7.5 V ~ 19 V
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: ST72F651, STDS75, STLM75
• Silicon Manufacturer: ST Micro
• Silicon Core Number: STLM75/STDS75 And ST72F651AR6
• Kit Application Type: Sensing - Temperature
• Application Sub Type: Temperature Sensor
• Kit Contents: Board
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Sensitivity: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 497-6238

ST72651AR6
INTERRUPTS (Cont’d)
Servicing Pending Interrupts
As several interrupts can be pending at the same
time, the interrupt to be taken into account is deter-
mined by the following two-step process:
– the highest software priority interrupt is serviced,
– if several interrupts have the same software pri-
Figure 26
Figure 26. Priority Decision Process
When an interrupt request is not serviced immedi-
ately, it is latched and then processed when its
software priority combined with the hardware pri-
ority becomes the highest one.
Note 1: The hardware priority is exclusive while
the software one is not. This allows the previous
process to succeed with only one interrupt.
Note 2: RESET, TRAP and TLI can be considered
as having the highest software priority in the deci-
sion process.
Different Interrupt Vector Sources
Two interrupt source types are managed by the
CPU interrupt controller: the non-maskable type
(RESET, TRAP, TLI) and the maskable type (ex-
ternal or from internal peripherals).
Non-Maskable Sources
These sources are processed regardless of the
state of the I1 and I0 bits of the CC register (see
Figure
registers (except for RESET), the corresponding
vector is loaded in the PC register and the I1 and
I0 bits of the CC are set to disable interrupts (level
3). These sources allow the processor to exit
HALT mode.
38/161
1
ority then the interrupt with the highest hardware
priority is serviced first.
PRIORITY SERVICED
HIGHEST HARDWARE
25). After stacking the PC, X, A and CC
Same
describes this decision process.
INTERRUPTS
SOFTWARE
PRIORITY
PENDING
HIGHEST SOFTWARE
PRIORITY SERVICED
Different
Doc ID 7215 Rev 4
■
This hardware interrupt occurs when a specific
edge is detected on the dedicated TLI pin.
Caution: A TRAP instruction must not be used in a
TLI service routine.
■
This software interrupt is serviced when the TRAP
instruction is executed. It will be serviced accord-
ing to the flowchart in
Caution: TRAP can be interrupted by a TLI.
■
The RESET source has the highest priority in the
CPU. This means that the first current routine has
the highest software priority (level 3) and the high-
est hardware priority.
See the RESET chapter for more details.
Maskable Sources
Maskable interrupt vector sources can be serviced
if the corresponding interrupt is enabled and if its
own interrupt software priority (in ISPRx registers)
is higher than the one currently being serviced (I1
and I0 in CC register). If any of these two condi-
tions is false, the interrupt is latched and thus re-
mains pending.
■
External interrupts allow the processor to exit from
HALT low power mode.
External interrupt sensitivity is software selectable
through the ISx bits in the MISCR1 and MISCR3
registers.
External interrupt triggered on edge will be latched
and the interrupt request automatically cleared
upon entering the interrupt service routine.
If several input pins of a group connected to the
same interrupt line are selected simultaneously,
these will be logically NANDed.
■
Usually the peripheral interrupts cause the Device
to exit from HALT mode except those mentioned in
the “Interrupt Mapping” table.
A peripheral interrupt occurs when a specific flag
is set in the peripheral status registers and if the
corresponding enable bit is set in the peripheral
control register.
The general sequence for clearing an interrupt is
based on an access to the status register followed
by a read or write to an associated register.
Note: The clearing sequence resets the internal
latch. A pending interrupt (i.e. waiting for being
serviced) will therefore be lost if the clear se-
quence is executed.
TLI (Top Level Hardware Interrupt)
TRAP (Non Maskable Software Interrupt)
RESET
External Interrupts
Peripheral Interrupts
Figure 25
as a TLI.