STEVAL-IFS003V1 STMicroelectronics, STEVAL-IFS003V1 Datasheet - Page 50

• Manufacturer Part Number: STEVAL-IFS003V1
• Description: BOARD STLM75/STDS75/ST72F651
• Manufacturer: STMicroelectronics

Specifications of STEVAL-IFS003V1

• Design Resources: STEVAL-IFS003V1 Gerber Files STEVAL-IFS003V1 Schematic STEVAL-IFS003V1 Bill of Materials
• Sensor Type: Temperature
• Sensing Range: -55°C ~ 125°C
• Interface: I²C
• Voltage - Supply: 7.5 V ~ 19 V
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: ST72F651, STDS75, STLM75
• Silicon Manufacturer: ST Micro
• Silicon Core Number: STLM75/STDS75 And ST72F651AR6
• Kit Application Type: Sensing - Temperature
• Application Sub Type: Temperature Sensor
• Kit Contents: Board
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Sensitivity: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 497-6238

ST72651AR6
I/O PORTS (Cont’d)
9.4 Register Description
DATA REGISTER (DR)
Port x Data Register
PxDR with x = A, B, C, D, E or F.
Read/Write
Reset Value: 0000 0000 (00h)
Bits 7:0 = D[7:0] Data register 8 bits.
The DR register has a specific behaviour accord-
ing to the selected input/output configuration. Writ-
ing the DR register is always taken into account
even if the pin is configured as an input; this allows
to always have the expected level on the pin when
toggling to output mode. Reading the DR register
always returns the digital value applied to the I/O
pin (pin configured as input).
DATA DIRECTION REGISTER (DDR)
Port x Data Direction Register
PxDDR with x = A, B, C, D, E or F.
Read/Write
Reset Value: 0000 0000 (00h)
Bits 7:0 = DD[7:0] Data direction register 8 bits.
The DDR register gives the input/output direction
configuration of the pins. Each bit is set and
cleared by software.
0: Input mode
1: Output mode
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1
DD7
D7
7
7
DD6
D6
DD5
D5
DD4
D4
DD3
D3
DD2
D2
DD1
D1
Doc ID 7215 Rev 4
DD0
D0
0
0
OPTION REGISTER (OR)
Port x Option Register
PxOR with x = A, C, D, or E
Read/Write
Reset Value: 0000 0000 (00h)
Bits 7:0 = O[7:0] Option register 8 bits.
For specific I/O pins, this register is not implement-
ed. In this case the DDR register is enough to se-
lect the I/O pin configuration.
The OR register allows to distinguish: in input
mode if the interrupt capability or the basic config-
uration is selected, in output mode if the push-pull
or open drain configuration is selected.
Each bit is set and cleared by software.
Input mode:
0: Floating input
1: Floating input with interrupt (ports A, C and D).
Output mode:
0: Output open drain (with P-Buffer deactivated)
1: Output push-pull
O7
For port E configuration, refer to
7
O6
O5
O4
O3
O2
Table
O1
14.
O0
0