STEVAL-IFS003V1 STMicroelectronics, STEVAL-IFS003V1 Datasheet - Page 143

• Manufacturer Part Number: STEVAL-IFS003V1
• Description: BOARD STLM75/STDS75/ST72F651
• Manufacturer: STMicroelectronics

Specifications of STEVAL-IFS003V1

• Design Resources: STEVAL-IFS003V1 Gerber Files STEVAL-IFS003V1 Schematic STEVAL-IFS003V1 Bill of Materials
• Sensor Type: Temperature
• Sensing Range: -55°C ~ 125°C
• Interface: I²C
• Voltage - Supply: 7.5 V ~ 19 V
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: ST72F651, STDS75, STLM75
• Silicon Manufacturer: ST Micro
• Silicon Core Number: STLM75/STDS75 And ST72F651AR6
• Kit Application Type: Sensing - Temperature
• Application Sub Type: Temperature Sensor
• Kit Contents: Board
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Sensitivity: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 497-6238

13.11 COMMUNICATION INTERFACE CHARACTERISTICS
13.11.1 SPI - Serial Peripheral Interface
Subject to general operating conditions for V
f
Figure 88. SPI Slave Timing Diagram with CPHA=0
Notes:
1. Data based on design simulation and/or characterisation results, not tested in production.
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has
its alternate function capability released. In this case, the pin status depends on the I/O port configuration.
3. Measurement points are done at CMOS levels: 0.3xV
OSC
Symbol
1/t
t
t
w(SCKH)
w(SCKL)
t
t
t
t
t
t
dis(SO)
t
t
t
t
t
t
r(SCK)
f(SCK)
su(SS)
t
su(MI)
t
h(MO)
f
su(SI)
a(SO)
h(SO)
v(MO)
MISO
MOSI
h(SS)
v(SO)
h(MI)
, and T
SCK
c(SCK)
h(SI)
SS
CPHA=0
CPOL=0
CPHA=0
CPOL=1
OUTPUT
INPUT
INPUT
A
SPI clock frequency
SPI clock rise and fall time
SS setup time
SS hold time
SCK high and low time
Data input setup time
Data input hold time
Data output access time
Data output disable time
Data output valid time
Data output hold time
Data output valid time
Data output hold time
unless otherwise specified.
see note 2
t
a(SO)
t
su(SS)
t
su(SI)
Parameter
MSB IN
t
t
w(SCKH)
w(SCKL)
MSB OUT
t
t
h(SI)
c(SCK)
Doc ID 7215 Rev 4
t
DD
v(SO)
DD
,
Master
Slave
Slave
Slave
Master
Slave
Master
Slave
Master
Slave
Slave
Slave
Slave (after enable edge)
Master (after enable edge)
BIT6 OUT
and 0.7xV
Refer to I/O port characteristics for more details on
the input/output alternate function characteristics
(SS, SCK, MOSI, MISO).
3)
Conditions
DD
BIT1 IN
.
t
h(SO)
f
f
CPU
CPU
=8MHz
=8MHz
t
t
r(SCK)
f(SCK)
f
CPU
LSB IN
0.0625
see I/O port pin description
Min
120
120
100
100
100
100
100
90
LSB OUT
0
0
0
0
/128
t
h(SS)
f
f
ST72651AR6
CPU
CPU
Max
120
240
120
120
2
4
/4
/2
t
dis(SO)
143/161
Unit
MHz
ns
note 2
see