ADE5166_08 AD [Analog Devices], ADE5166_08 Datasheet - Page 96

• Manufacturer Part Number: ADE5166_08
• Description: Single-Phase Energy Measurement IC with 8052 MCU, RTC, and LCD Driver
• Manufacturer: AD [Analog Devices]

ADE5166/ADE5169
BLINK MODE
Blink mode is enabled by setting the BLINKEN bit (Bit 5) in the
LCD configuration SFR (LCDCON, Address 0x95). This mode
is used to alternate between the LCD on state and LCD off state
so that the LCD screen appears to blink. There are two blinking
modes: a software controlled blink mode and an automatic
blink mode.
Software Controlled Blink Mode
The LCD blink rate can be controlled by user code with the
BLKMOD bits (Bits[7:6]) in the LCD clock SFR (LCDCLK,
Address 0x96) by toggling the bits to turn the display on and off
at a rate determined by the MCU code.
Automatic Blink Mode
There are five blink rates. These blink rates are selected by the
BLKMOD bits (Bits[7:6]) and the BLKFREQ bits (Bits[5:4]) bits
in the LCD clock SFR (LCDCLK, Address 0x96); see Table 94.
SCROLLING MODE
The ADE5166/ADE5169 provide the possibility to have four
screens in memory. The LCD driver can use any of these screens
by setting the SCREEN_SEL bits in the LCD Configuration Y SFR
(LCDCONY, Address 0xB1) and clearing the refresh bit (Bit 0)
in the same register. The software scrolling of the screens can
then be achieved by a one-command instruction.
Automatic Scrolling Mode
The ADE5166/ADE5169 also provide an automatic scrolling
between the screens using the five available blink rates. This
mode is enabled by setting bit AUTOSCREENSCROLL (Bit 7)
in the LCD Configuration Y SFR (LCDCONY, Address 0xB1)
and also the BLINKEN bit (Bit 5) in the LCD configuration SFR
(LCDCON, Address 0x95). To allow the scrolling frequency to
be selected, the BLKMOD bits (Bits[7:6]) in the LCD clock SFR
(LCDCLK, Address 0x96) should both be set to 1. The scrolling
rates are then selected by the BLKFREQ bits (Bits[5:4]) in the
LCD clock SFR (LCDCLK, Address 0x96); see Table 94. Auto-
matic scrolling mode is available in all operating modes.
DISPLAY ELEMENT CONTROL
Four banks of 15 bytes of data memory located in the LCD module
control the on or off state of each segment of the LCD. The LCD
data memory is stored in Address 0 through Address 14 in the
LCD module, with two extra bits defining which one of the four
screens is being addressed.
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Each byte configures the on and off states of two segment lines.
The LSBs store the state of the even numbered segment lines,
and the MSBs store the state of the odd numbered segment lines.
For example, LCD Data Address 0 refers to segment Line 1 and
Line 0 (see Table 101). Note that the LCD data memory is
maintained in the PSM2 operating mode.
The LCD data memory is accessed indirectly through the LCD
pointer SFR (LCDPTR, Address 0xAC) and LCD data SFR
(LCDDAT, Address 0xAE). Moving a value to the LCDPTR SFR
selects the LCD screen and data byte to be accessed and initiates
a read or write operation (see Table 98).
Writing to LCD Data Registers
To update the LCD data memory, first set the LSB of the LCD
Configuration Y SFR (LCDCONY, Address 0xB1) to freeze the
data being displayed on the LCD while updating it. This operation
ensures that the data displayed on the screen does not change
while the data is being changed. Then, move the data to the
LCD data SFR (LCDDAT, Address 0xAE) prior to accessing the
LCD pointer SFR (LCDPTR, Address 0xAC). The address of the
LCD screen should be consistent with the data changed. When the
MSB of the LCD pointer SFR (LCDPTR, Address 0xAC) is set, the
content of the LCD data SFR (LCDDAT, Address 0xAE) is trans-
ferred to the internal LCD data memory designated by the address
in the LCD pointer SFR (LCDPTR, Address 0xAC) and the
screen designator. Clear the LSB of the LCD Configuration Y SFR
(LCDCONY, Address 0xB1) when all of the data memory has been
updated to allow the use of the new LCD setup for display.
Sample 8052 code to update the segments attached to Pin FP10
and Pin FP11 on Screen 1 is as follows:
ORL
MOV
MOV
ANL
Reading LCD Data Registers
When the MSB of the LCD pointer SFR (LCDPTR, Address 0xAC)
is cleared, the content of the LCD data memory of the correspond-
ing screen designated by LCDPTR is transferred to the LCD data
SFR (LCDDAT, Address 0xAE).
Sample 8052 code to read the contents of LCD Data Memory
Address 0x07 on Screen 1, which holds the on and off state of
the segments attached to FP14 and FP15, is as follows.
MOV
MOV
LCDCONY,#01h ;start updating the data
LCDDAT,#FFh
LCDPTR,#80h OR 05h
LCDCONY,#0FEh ;update finished
LCDPTR,#07h
R1, LCDDAT