ADE5166_08 AD [Analog Devices], ADE5166_08 Datasheet - Page 138

• Manufacturer Part Number: ADE5166_08
• Description: Single-Phase Energy Measurement IC with 8052 MCU, RTC, and LCD Driver
• Manufacturer: AD [Analog Devices]

ADE5166/ADE5169
Table 159. I
Bit
7
6
5
4
[3:2]
1
0
READ AND WRITE OPERATIONS
Figure 109 and Figure 110 depict I
respectively. Note that the LSB of the I2CADR SFR (Address 0xE9)
is used to select whether a read or write operation is performed
on the slave device. During the read operation, the master acknowl-
edges are generated automatically by the I
master generated no acknowledge (NACK) before the end of a
read operation is also automatically generated after the I2CRCT
bits in the I2CMOD SFR (Address 0xE8[4:0]) have been read from
the slave. If the I2CADR register is updated during a
transmission, instead of generating a stop at the end of the read
or write operation, the master generates a start condition and
continues with the next communication.
SDATA
SCLK
START BY
MASTER
Mnemonic
I2CBUSY
I2CNOACK
I2CRxIRQ
I2CTxIRQ
I2CFIFOSTAT
I2CACC_ERR
I2CTxWR_ERR
A6
2
1
C Interrupt Status Register SFR (SPI2CSTAT, Address 0xEA)
SE
A5
RIAL BUS ADDRESS BYTE
SDATA
SCLK
A4
START BY
MASTER
FRAME 1
A3
A2
Default
0
0
0
0
0
0
0
A6
1
A1
2
C read and write operations,
A5
SERIAL BUS ADDRESS BYTE
A0
A4
Description
This bit is set to Logic 1 when the I
I
does not send an acknowledgement. The I
Write a 0 to this bit to clear it.
I
Write a 0 to this bit to clear it.
I
Write a 0 to this bit to clear it.
Status bits for 3- or 4-byte deep I
used in I
I2CFIFOSTAT
00
01
10
11
Set when trying to write and read at the same time. Write a 0 to this bit to clear it.
Set when a write was attempted when the I
R/W
2
2
2
C no acknowledgement transmit interrupt. This bit is set to Logic 1 when the slave device
C receive interrupt. This bit is set to Logic 1 when the receive FIFO is not empty.
C transmit interrupt. This bit is set to Logic 1 when the transmit FIFO is empty.
2
C peripheral. The
ACK BY
SLAVE
FRAME 1
A3
9
2
A2
C communication (receive or transmit) because only one FIFO is active at a time.
D7
1
A1
D6
DATA BYTE 1 FROM MASTER
Figure 110. I
Figure 109. I
A0
D5
Rev. 0 | Page 138 of 148
R/W
D4
ACK BY
SLAVE
FRAME 2
Result
FIFO empty
Reserved
FIFO half full
FIFO full
D3
2
9
2
C Write Operation
C Read Operation
D2
D7
1
2
C FIFO. The FIFO monitored in these two bits is the one currently
2
D1
Reading the SPI/I
Address 0x9B)
Reading the SPI2CRx SFR should be done with a 2-cycle
instruction, such as
Mov a, spi2crx or Mov R0, spi2crx
A 3-cycle instruction, such as
Mov 3dh, spi2crx
does not transfer the right data into RAM Address 0x3D.
D6
C interface is used. When set, the Tx FIFO is emptied.
DATA BYTE 1 FROM MASTER
D0
D5
ACK BY
MASTER
2
9
C communication is stopped after this event.
D4
2
C transmit FIFO was full. Write a 0 to this bit to clear it.
FRAME 2
D3
D2
D7
1
2
C Receive Buffer SFR (SPI2CRx,
D6
D1
DATA BYTE N FROM SLAVE
D5
D0
ACK BY
SLAVE
D4
9
FRAME N + 1
D3
STOP BY
MASTER
D2
D1
D0
NACK BY
MASTER
.
9
STOP BY
MASTER