ADE5166_08 AD [Analog Devices], ADE5166_08 Datasheet - Page 82

• Manufacturer Part Number: ADE5166_08
• Description: Single-Phase Energy Measurement IC with 8052 MCU, RTC, and LCD Driver
• Manufacturer: AD [Analog Devices]

ADE5166/ADE5169
Mnemonic
Miscellaneous
READ-MODIFY-WRITE INSTRUCTIONS
Some 8052 instructions read the latch and others read the pin.
The state of the pin is read for instructions that input a port bit.
Instructions that read the latch rather than the pins are the ones
that read a value, possibly change it, and rewrite it to the latch.
Because these instructions involve modifying the port, it is
assumed that the pins being modified are outputs, so the output
state of the pin is read from the latch. This prevents a possible
misinterpretation of the voltage level of a pin. For example, if a
port pin is used to drive the base of a transistor, a 1 is written to
the bit to turn on the transistor. If the CPU reads the same port
bit at the pin rather than the latch, it reads the base voltage of
the transistor and interprets it as Logic 0. Reading the latch
rather than the pin returns the correct value of 1.
The instructions that read the latch rather than the pins are
called read-modify-write instructions and are listed in Table 68.
When the destination operand is a port or a port bit, these
instructions read the latch rather than the pin.
Table 68. Read-Modify-Write Instructions
Instruction
ANL
ORL
XRL
JBC
CPL
INC
DEC
DJNZ
MOV PX.Y, C
CLR PX.Y
SETB PX.Y
1
These instructions read the port byte (all eight bits), modify the addressed
bit, and write the new byte back to the latch.
JNC rel
JZ rel
JNZ rel
DJNZ Rn, rel
LJMP
LCALL addr16
JB bit, rel
JNB bit, rel
JBC bit, rel
CJNE A, dir, rel
CJNE A, #data, rel
CJNE Rn, #data, rel
CJNE @Ri, #data, rel
DJNZ dir, rel
NOP
1
1
1
Example
ANL P0, A
ORL P1, A
XRL P2, A
JBC P1.1, LABEL
CPL P2.0
INC P2
DEC P2
DJNZ P0, LABEL
MOV P0.0, C
CLR P0.0
SETB P0.0
Description
Logic AND
Logic OR
Logic XOR
Jump if Bit = 1 and clear bit
Complement bit
Increment
Decrement
Decrement and jump if not zero
Move carry to Bit Y of Port X
Clear Bit Y of Port X
Set Bit Y of Port X
Compare register, immediate JNE relative
Description
Jump on carry = 0
Jump on accumulator = 0
Jump on accumulator ≠ 0
Decrement register, JNZ relative
Long jump unconditional
Long jump to subroutine
Jump on direct bit = 1
Jump on direct bit = 0
Jump on direct bit = 1 and clear
Compare A, direct JNE relative
Compare A, immediate JNE relative
Compare indirect, immediate JNE relative
Decrement direct byte, JNZ relative
No operation
Rev. 0 | Page 82 of 148
INSTRUCTIONS THAT AFFECT FLAGS
Many instructions explicitly modify the carry bit, such as the
MOV C bit and CLR C instructions. Other instructions that
affect status flags are listed in this section.
ADD A, Source
This instruction adds the source to the accumulator. No status
flags are referenced by the instruction.
Table 69. ADD A (Source) Affected Status Flags
Flag
C
OV
AC
ADDC A, Source
This instruction adds the source and the carry bit to the accu-
mulator. The carry status flag is referenced by the instruction.
Table 70. ADDC A (Source) Affected Status Flags
Flag
C
OV
AC
Description
Set if there is a carry out of Bit 7. Cleared otherwise. Used
to indicate an overflow if the operands are unsigned.
Set if there is a carry out of Bit 6 or a carry out of Bit 7, but
not if both are set. Used to indicate an overflow for
signed addition. This flag is set if two positive operands
yield a negative result or if two negative operands yield a
positive result.
Set if there is a carry out of Bit 3. Cleared otherwise.
Description
Set if there is a carry out of Bit 7. Cleared otherwise. Used
to indicate an overflow if the operands are unsigned.
Set if there is a carry out of Bit 6 or a carry out of Bit 7, but
not if both are set. Used to indicate an overflow for
signed addition. This flag is set if two positive operands
yield a negative result or if two negative operands yield a
positive result.
Set if there is a carry out of Bit 3. Cleared otherwise.
Bytes
2
2
2
2
3
3
3
3
3
3
3
3
3
3
1
Cycles
3
3
3
3
4
4
4
4
4
4
4
4
4
4
1