ADE5166_08 AD [Analog Devices], ADE5166_08 Datasheet - Page 50

• Manufacturer Part Number: ADE5166_08
• Description: Single-Phase Energy Measurement IC with 8052 MCU, RTC, and LCD Driver
• Manufacturer: AD [Analog Devices]

ADE5166/ADE5169
Peak Detection
The ADE5166/ADE5169 can also be programmed to detect when
the absolute value of the voltage or current channel exceeds a
specified peak value. Figure 54 illustrates the behavior of the
peak detection for the voltage channel. Both voltage and current
channels are monitored at the same time.
Figure 54 shows a line voltage exceeding a threshold that is set
in the voltage peak register (VPKLVL[15:0], Address 0x16). The
voltage peak event is recorded by setting the PKV flag in the
Interrupt Status 3 SFR (MIRQSTH, Address 0xDE). If the PKV
enable bit (Bit 3) is set in the Interrupt Enable 3 SFR (MIRQENH,
Address 0xDB), the 8052 core has a pending ADE interrupt.
Similarly, the current peak event is recorded by setting the PKI flag
(Bit 4) in Interrupt Status 3 SFR (MIRQSTH, Address 0xDE). The
ADE interrupt stays active until the PKV or PKI status bit is cleared
(see the Energy Measurement Interrupts section).
Peak Level Set
The contents of the VPKLVL (Address 0x16) and IPKLVL
(Address 0x15) registers are compared to the absolute value of the
voltage and 2 MSBs of the current channel, respectively. Thus,
for example, the nominal maximum code from the current channel
ADC with a full-scale signal is 0x28F5C2 (see the Current Channel
ADC section). Therefore, writing 0x28F5 to the IPKLVL register
puts the current channel, peak detection level at full scale and
sets the current peak detection to its least sensitive value. Writing
0x00 puts the current channel detection level at 0. The detection
is done by comparing the contents of the IPKLVL register to the
incoming current channel sample. The PKI flag indicates that
the peak level is exceeded. If the PKI or PKV bit is set in the
Interrupt Enable 3 SFR (MIRQENH, Address 0xDB), the 8052
core has a pending ADE interrupt.
Peak Level Record
Each ADE5166/ADE5169 records the maximum absolute value
reached by the current and voltage channels in two different
registers, IPEAK (Address 0x17) and VPEAK (Address 0x19),
respectively. Each register is a 24-bit unsigned register that is
updated each time the absolute value of the waveform sample
IN MIRQSTH SFR
PKV INTERRUPT
RESET BIT PKV
VPKLVL[15:0]
FLAG
V
2
Figure 54. Peak Level Detection
PKV RESET
LOW WHEN
MIRQSTH SFR
IS READ
Rev. 0 | Page 50 of 148
from the corresponding channel is above the value stored in the
IPEAK or VPEAK register. The contents of the VPEAK register
correspond to the maximum absolute value observed on the
voltage channel input. The contents of IPEAK and VPEAK
represent the maximum absolute value observed on the current
and voltage input, respectively. Reading the RSTIPEAK
(Address 0x18) and RSTVPEAK (Address 0x17) registers clears
their respective contents after the read operation.
PHASE COMPENSATION
The ADE5166/ADE5169 must work with transducers that can
have inherent phase errors. For example, a phase error of 0.1° to
0.3° is not uncommon for a current transformer (CT). These phase
errors can vary from part to part, and they must be corrected to
perform accurate power calculations. The errors associated with
phase mismatch are particularly noticeable at low power factors.
The ADE5166/ADE5169 provide a means of digitally calibrating
these small phase errors. The part allows a small time delay or
time advance to be introduced into the signal processing chain
to compensate for small phase errors. Because the compensation
is in time, this technique should be used only for small phase
errors in the range of 0.1° to 0.5°. Correcting large phase errors
using a time shift technique can introduce significant phase errors
at higher harmonics.
The phase calibration register (PHCAL[7:0], Address 0x10) is a
twos complement, signed, single-byte register that has values
ranging from 0x82 (−126d) to 0x68 (+104d).
The PHCAL register is centered at 0x40, meaning that writing
0x40 to the register gives 0 delay. By changing this register, the
time delay in the voltage channel signal path can change from
−231.93 μs to +48.83 μs (MCLK = 4.096 MHz). One LSB is equiv-
alent to a 1.22 μs (4.096 MHz/5) time delay or advance. A line
frequency of 60 Hz gives a phase resolution of 0.026° at the
fundamental (that is, 360° × 1.22 μs × 60 Hz).
Figure 55 illustrates how the phase compensation is used to
remove a 0.1° phase lead in the current channel due to the
external transducer. To cancel the lead (0.1°) in the current
channel, a phase lead must also be introduced into the voltage
channel. The resolution of the phase adjustment allows the
introduction of a phase lead in increments of 0.026°. The phase
lead is achieved by introducing a time advance into the voltage
channel. A time advance of 4.88 μs is made by writing −4 (0x3C)
to the time delay block, thus reducing the amount of time delay
by 4.88 μs, or equivalently, a phase lead of approximately 0.1° at a
line frequency of 60 Hz (0x3C represents −4 because the register is
centered with 0 at 0x40).