ADE5166_08 AD [Analog Devices], ADE5166_08 Datasheet - Page 134

• Manufacturer Part Number: ADE5166_08
• Description: Single-Phase Energy Measurement IC with 8052 MCU, RTC, and LCD Driver
• Manufacturer: AD [Analog Devices]

ADE5166/ADE5169
Table 155. SPI Interrupt Status SFR (SPISTAT, Address 0xEA)
Bit
7
6
5
4
3
2
1
0
SPI PINS
MISO (Master In, Slave Out Data I/O Pin)
The MISO (P0.5/MISO/ZX) pin is configured as an input line
in master mode and as an output line in slave mode. The MISO
line on the master (data in) should be connected to the MISO
line in the slave device (data out). The data is transferred as
byte-wide (8-bit) serial data, MSB first.
MOSI (Master Out, Slave In Pin)
The MOSI (P0.4/MOSI/SDATA) pin is configured as an output
line in master mode and as an input line in slave mode. The MOSI
line on the master (data out) should be connected to the MOSI
line in the slave device (data in). The data is transferred as byte-
wide (8-bit) serial data, MSB first.
Mnemonic
BUSY
MMERR
SPIRxOF
SPIRxIRQ
SPIRxBF
SPITxUF
SPITxIRQ
SPITxBF
Default
0
0
0
0
0
0
0
0
Description
SPI peripheral busy flag.
BUSY
0
1
SPI multimaster error flag.
MMERR
0
1
SPI receive overflow error flag. Reading the SPI2CRx SFR clears this bit.
SPIRxOF
0
1
SPI receive mode interrupt flag. Reading the SPI2CRx SFR clears this bit.
SPIRxIRQ
0
1
1
Status bit for SPI Rx buffer. When set, the Rx FIFO is full. A read of the SPI2CRx clears this flag.
Status bit for SPI Tx buffer. When set, the Tx FIFO is underflowing and data can be written into SPI2CTx
(Address 0x9A). Write a 0 to this bit to clear it.
SPI transmit mode interrupt flag. Writing new data to the SPI2CTx SFR clears this bit.
SPITxIRQ
0
1
1
Status bit for the SPI Tx buffer. When set, the SPI Tx buffer is full. Write a 0 to this bit to clear it.
Result
The SPI peripheral is idle.
The SPI peripheral is busy transferring data in slave or master mode.
Result
A multiple master error has not occurred.
If the SS_EN bit (SPIMOD1, Address 0xE8) is set, enabling the slave select input and
asserting the SS pin while the SPI peripheral is transferring data as a master, this flag is
raised to indicate the error. Write a 0 to this bit to clear it.
TIMODE
X
1
TIMODE
X
0
1
TIMODE
X
0
1
Result
The SPI2CRx SFR (Address 0x9B) contains valid data.
This bit is set if the SPI2CRx SFR is not read before the end of the next byte
transfer. If the RxOFW bit (SPIMOD1, Address 0xE8) is set and this condition
occurs, SPI2CRx is overwritten.
Result
The SPI2CRx register does not contain new data.
This bit is set when the SPI2CRx register contains new data. If the SPI/I
enabled, an interrupt is generated when this bit is set. If the SPI2CRx register is
not read before the end of the current byte transfer, the transfer stops and the
SS pin is deasserted.
The SPI2CRx register contains new data.
Result
The SPI2CTx SFR is full.
The SPI2CTx SFR is empty.
This bit is set when the SPI2CTx SFR is empty. If the SPI/I
an interrupt is generated when this bit is set. If new data is not written into the
SPI2CTx SFR before the end of the current byte transfer, the transfer stops, and
the SS pin is deasserted. Write a 0 to this bit to clear it.
Rev. 0 | Page 134 of 148
SCLK (Serial Clock I/O Pin)
The master serial clock (SCLK) is used to synchronize the data
being transmitted and received through the MOSI and MISO
data lines. The SCLK (P0.6/SCLK/T0) pin is configured as an
output in master mode and as an input in slave mode.
In master mode, the bit rate, polarity, and phase of the clock are
controlled by SPI Configuration SFR 1 (SPIMOD1, Address 0xE8)
and SPI Configuration SFR 2 (SPIMOD2, Address 0xE9).
In slave mode, the SPI Configuration SFR 2 (SPIMOD2,
Address 0xE9) must be configured with the phase and polarity
of the expected input clock.
In both master and slave modes, the data is transmitted on one
edge of the SCLK signal and sampled on the other. It is important,
therefore, that the SPICPHA and SPICPOL bits be configured
the same for the master and slave devices.
2
C interrupt is enabled,
2
C interrupt is