ADE5166_08 AD [Analog Devices], ADE5166_08 Datasheet - Page 140

• Manufacturer Part Number: ADE5166_08
• Description: Single-Phase Energy Measurement IC with 8052 MCU, RTC, and LCD Driver
• Manufacturer: AD [Analog Devices]

ADE5166/ADE5169
I/O PORTS
PARALLEL I/O
The ADE5166/ADE5169 use three input/output ports to
exchange data with external devices. In addition to performing
general-purpose I/O, some are capable of driving an LCD or
performing alternate functions for the peripherals available on-
chip. In general, when a peripheral is enabled, the pins associated
with it cannot be used as a general-purpose I/O. The I/O port
can be configured through the SFRs listed in Table 160.
Table 160. I/O Port SFRs
SFR
P0
P1
P2
EPCFG
PINMAP0
PINMAP1
PINMAP2
The three bidirectional I/O ports have internal pull-ups that can
be enabled or disabled individually for each pin. The internal
pull-ups are enabled by default. Disabling an internal pull-up
causes a pin to become open drain. Weak internal pull-ups are
configured through the PINMAPx SFRs.
Figure 112 shows a typical bit latch and I/O buffer for an I/O pin.
The bit latch (one bit in the SFR of each port) is represented as a
Type D flip-flop, which clocks in a value from the internal bus
in response to a write-to-latch signal from the CPU. The Q out-
put of the flip-flop is placed on the internal bus in response to a
read latch signal from the CPU. The level of the port pin itself is
placed on the internal bus in response to a read pin signal from
the CPU. Some instructions that read a port activate the read
latch signal, and others activate the read pin signal. See the
Read-Modify-Write Instructions section for details.
INTERNAL
TO LATCH
LATCH
WRITE
READ
READ
BUS
PIN
Address
0x80
0x90
0xA0
0x9F
0xB2
0xB3
0xB4
Figure 112. Port 0 Bit Latch and I/O Buffer
LATCH
CL
D
Q
Q
ALTERNATE
ALTERNATE
FUNCTION
FUNCTION
Bit Addressable
Yes
Yes
Yes
No
No
No
No
OUTPUT
INPUT
DV
DD
CLOSED: PINMAPx.x = 0
OPEN: PINMAPx.x = 1
INTERNAL
PULL-UP
Description
Port 0 register
Port 1 register
Port 2 Register
Extended port
configuration
Port 0 weak
pull-up enable
Port 1 weak
pull-up enable
Port 2 weak
pull-up enable
Px.x
PIN
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Weak Internal Pull-Ups Enabled
A pin with weak internal pull-up enabled is used as an input by
writing a 1 to the pin. The pin is pulled high by the internal pull-
ups, and the pin is read using the circuitry shown in Figure 112.
If the pin is driven low externally, it sources current because of
the internal pull-ups.
A pin with internal pull-up enabled is used as an output by writing
a 1 or a 0 to the pin to control the level of the output. If a 0 is
written to the pin, it drives a logic low output voltage (V
is capable of sinking 1.6 mA.
Open Drain (Weak Internal Pull-Ups Disabled)
When the weak internal pull-up on a pin is disabled, the pin
becomes open drain. Use this open-drain pin as a high impedance
input by writing a 1 to the pin. The pin is read using the circuitry
shown in Figure 112. The open-drain option is preferable for
inputs because it draws less current than the internal pull-ups
that were enabled.
38 kHz Modulation
Every ADE5166/ADE5169 provides a 38 kHz modulation signal.
The 38 kHz modulation is accomplished by internally XOR’ing
the level written to the I/O pin with a 38 kHz square wave. Then,
when a 0 is written to the I/O pin, it is modulated as shown in
Figure 113.
Uses for this 38 kHz modulation include IR modulation of
a UART transmit signal or a low power signal to drive an LED.
The modulation can be enabled or disabled with the MOD38EN
bit (Bit 4) in the CFG SFR (Address 0xAF). The 38 kHz modu-
lation is available on eight pins, selected by the MOD38[7:0] bits in
the extended port configuration SFR (EPCFG, Address 0x9F).
38kHz MODULATION
38kHz MODULATED
LEVEL WRITTEN
OUTPUT PIN
TO MOD38
SIGNAL
Figure 113. 38 kHz Modulation
OL
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