ADE5166_08 AD [Analog Devices], ADE5166_08 Datasheet - Page 87

• Manufacturer Part Number: ADE5166_08
• Description: Single-Phase Energy Measurement IC with 8052 MCU, RTC, and LCD Driver
• Manufacturer: AD [Analog Devices]

INTERRUPT FLAGS
The interrupt flags and status flags associated with the interrupt vectors are shown in Table 84 and Table 85, respectively. Most of the
interrupts have flags associated with them.
Table 84. Interrupt Flags
Interrupt Source
IE0
TF0
IE1
TF1
RI + TI
RI2 + TI2
TF2 + EXF2
ITEMP (Temperature ADC)
IPSM (Power Supply)
IADE (Energy Measurement DSP)
Table 85. Status Flags
Interrupt Source
ITEMP (Temperature ADC)
ISPI/I2CI
IRTC (RTC Interval Timer)
WDT (Watchdog Timer)
1
A functional block diagram of the interrupt system is shown in
Figure 84. Note that the PSM interrupt is the only interrupt in
the highest priority level.
If an external wake-up event occurs to wake the ADE5166/
ADE5169 from PSM2 mode, a pending external interrupt is
generated. When the EX0 bit (Bit 0) or the EX1 bit (Bit2) in the
interrupt enable SFR (IE, Address 0xA8) is set to enable external
interrupts, the program counter is loaded with the IE0 or IE1
interrupt vector. The IE0 and IE1 interrupt flags (Bit 1 and Bit 3,
respectively) in the Timer/Counter 0 and Timer/Counter 1 control
SFR (TCON, Address 0x88) are not affected by events that occur
when the 8052 MCU core is shut down during PSM2 mode (see
the Power Supply Management (PSM) Interrupt section).
The temperature ADC and I
that pending interrupts cannot be cleared without entering their
respective interrupt service routines. Clearing the I
bits in the SPI interrupt status SFR (SPISTAT, Address 0xEA)
does not cancel a pending I
There is no specific flag for ISPI/I2CI; however, all flags for SPI2CSTAT need to be read to assess the reason for the interrupt.
2
C/SPI interrupt. These interrupts
2
C/SPI interrupts are latched such
Flag
N/A
SPI2CSTAT
SPI2CSTAT
TIMECON.6
TIMECON.2
WDCON.2
Flag
TCON.1
TCON.5
TCON.3
TCON.7
SCON.1
SCON.0
SCON2.1
SCON2.0
T2CON.7
T2CON.6
N/A
IPSMF.6
MIRQSTL.7
1
IE0
TF0
IE1
TI
TI2
RI2
TF2
EXF2
FPSM
Bit Name
TF1
RI
N/A
ADEIRQFLAG
Bit Address
N/A
N/A
N/A
ALFLAG
ITFLAG
WDS
2
C/SPI status
Rev. 0 | Page 87 of 148
Description
External Interrupt 0.
Timer 0.
External Interrupt 1.
Timer 1.
Transmit interrupt.
Receive interrupt.
Transmit 2 interrupt
Receive 2 interrupt
Timer 2 overflow flag.
Timer 2 external flag.
Temperature ADC interrupt. Does not have an interrupt flag associated with it.
PSM interrupt flag.
Read MIRQSTH, MIRQSTM, MIRQSTL.
Temperature ADC interrupt. Does not have a status flag associated with it.
SPI interrupt status register.
I
RTC alarm flag.
RTC interrupt flag.
Watchdog timeout flag.
Description
2
C interrupt status register.
remain pending until the I
Their respective interrupt service routines are entered shortly
thereafter.
The RTC interrupts are driven by the alarm and interval flags.
Pending RTC interrupts can be cleared without entering the
interrupt service routine, by clearing the corresponding RTC
flag in software. Entering the interrupt service routine alone
does not clear the RTC interrupt.
Figure 84 shows how the interrupts are cleared when the inter-
rupt service routines are entered. Some interrupts with multiple
interrupt sources are not automatically cleared; specifically, the
PSM, ADE, UART, UART2 and Timer 2 interrupt vectors. Note
that the INT0 and INT1 interrupts are cleared only if the external
interrupt is configured to be triggered by a falling edge by setting
IT0 (Bit 0) in the Timer/Counter 0 and Timer/Counter 1 control
SFR (TCON, Address 0x88). If INT0 or INT1 is configured to
interrupt on a low level, the interrupt service routine is
reentered until the respective pin goes high.
2
C/SPI interrupt vectors are enabled.
ADE5166/ADE5169