DS26518GNB1+ Maxim Integrated Products, DS26518GNB1+ Datasheet - Page 76

• Manufacturer Part Number: DS26518GNB1+
• Description: IC TXRX T1/E1/J1 8PRT 256-CSBGA
• Manufacturer: Maxim Integrated Products
• Type: Transceiverr

Specifications of DS26518GNB1+

• Number Of Drivers/receivers: 8/8
• Protocol: T1/E1/J1
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 256-CSBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.10.1.2
The lower 7 bits of the Receive HDLC-64 Packet Bytes Available Register (RHPBA) indicates the number of bytes
(0 to 64) that can be read from the receive FIFO. The value indicated by this register informs the host as to how
many bytes can be read from the receive FIFO without going past the end of a message. This value refers to one
of four possibilities: the first part of a packet, the continuation of a packet, the last part of a packet, or a complete
packet. After reading the number of bytes indicated by this register, the host then checks the HDLC-64 status
registers for detailed message status.
If the value in the
MSB of the RHPBA register returns a value of 1. This indicates that the host can safely read the number of bytes
returned by the lower 7 bits of the RHPBA register, but there is no need to check the information register since the
packet has not yet terminated (successfully or otherwise).
9.10.1.3
RRTS5, RLS5, and
occurred (or is occurring), the appropriate bit in one of these registers will be set to a one. Some of the bits in these
registers are latched and some are real-time bits that are not latched. This section contains register descriptions
that list which bits are latched and which are real-time. With the latched bits, when an event occurs and a bit is set
to a one, it will remain set until the user reads and clears that bit. The bit will be cleared when a 1 is written to the
bit and it will not be set again until the event has occurred again. The real-time bits report the current instantaneous
conditions that are occurring and the history of these bits is not latched.
Like the other latched status registers, the user will follow a read of the status bit with a write. The byte written to
the register will inform the device which of the latched bits the user wishes to clear (the real-time bits are not
affected by writing to the status register). The user will write a byte to one of these registers, with a one in the bit
positions he or she wishes to clear and a zero in the bit positions he or she does not wish to clear.
The HDLC-64 status registers
signal. Each of the events in this register can be either masked or unmasked from the interrupt pin via the
HDLC-64 interrupt mask registers
The INTB pin will be allowed to return high (if no other interrupts are present) when the user reads the event bit that
caused the interrupt to occur.
9.10.1.4
The HDLC-64 status registers in the DS26518 allow for flexible software interface to meet the user’s preferences.
When receiving HDLC-64 messages, the host can choose to be interrupt driven, to poll to desired status registers,
or a combination of polling and interrupt processes can be used.
the DS26518 HDLC-64 receiver.
HDLC-64 Status and Information
Receive Packet Bytes Available
Receive HDLC-64 Example
RHPBA
TLS2
register refers to the beginning portion of a message or continuation of a message, the
provide status information for the HDLC-64 controller. When a particular event has
RLS5
RIM5
and
and TIM2. Interrupts will force the INTB signal low when the event occurs.
TLS2
have the ability to initiate a hardware interrupt via the INTB output
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Figure 9-17
shows an example routine for using