DS26518GNB1+ Maxim Integrated Products, DS26518GNB1+ Datasheet - Page 183
DS26518GNB1+
Manufacturer Part Number
DS26518GNB1+
Description
IC TXRX T1/E1/J1 8PRT 256-CSBGA
Manufacturer
Maxim Integrated Products
Type
Transceiverr
Datasheet
1.DS26518GNB1.pdf
(312 pages)
Specifications of DS26518GNB1+
Number Of Drivers/receivers
8/8
Protocol
T1/E1/J1
Voltage - Supply
3.135 V ~ 3.465 V
Mounting Type
Surface Mount
Package / Case
256-CSBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Note: All bits in this register are latched and can cause interrupts
Bit 5: Receive FIFO Overrun (ROVR). Set when the receive HDLC-64 controller has terminated packet reception
because the FIFO buffer is full.
Bit 4: Receive HDLC-64 Opening Byte Event (RHOBT). Set when the next byte available in the receive FIFO is
the first byte of a message.
Bit 3: Receive Packet End Event (RPE). Set when the HDLC-64 controller detects either the finish of a valid
message (i.e., CRC check complete) or when the controller has experienced a message fault such as a CRC
checking error, or an overrun condition, or an abort has been seen. This is a latched bit and will be cleared when
read.
Bit 2: Receive Packet Start Event (RPS). Set when the HDLC-64 controller detects an opening byte. This is a
latched bit and will be cleared when read.
Bit 1: Receive FIFO Above High Watermark Set Event (RHWMS). Set when the receive 64-byte FIFO crosses
the high watermark as defined by the Receive HDLC-64 FIFO Control Register (RHFC). Rising edge detect of
RHWM.
Bit 0: Receive FIFO Not Empty Set Event (RNES). Set when the receive FIFO has transitioned from “empty” to
“not empty” (at least one byte has been put into the FIFO). Rising edge detect of RNE.
—
7
0
RLS5
Receive Latched Status Register 5 (HDLC-64)
094h + (200h x (n - 1)) : where n = 1 to 8
—
6
0
ROVR
5
0
RHOBT
183 of 312
0
4
.
RPE
3
0
RPS
2
0
RHWMS
1
0
RNES
0
0
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