DS26518GNB1+ Maxim Integrated Products, DS26518GNB1+ Datasheet - Page 199

• Manufacturer Part Number: DS26518GNB1+
• Description: IC TXRX T1/E1/J1 8PRT 256-CSBGA
• Manufacturer: Maxim Integrated Products
• Type: Transceiverr

Specifications of DS26518GNB1+

• Number Of Drivers/receivers: 8/8
• Protocol: T1/E1/J1
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 256-CSBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Note: All bits in this register are real time.
Bits 6 to 4: Receive Packet Status (PS[2:0]). These are real-time bits indicating the status as of the last read of
the receive FIFO.
Bit 1: Receive FIFO Above High Watermark Condition (RHWM). Set when the receive 64-byte FIFO fills beyond
the high watermark as defined by the Receive HDLC-64 FIFO Control Register (RHFC). This is a real-time bit.
Bit 0: Receive FIFO Not Empty Condition (RNE). Set when the receive 64-byte FIFO has at least one byte
available for a read. This is a real-time bit.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: Message Status (MS)
Bits 6 to 0: Receive FIFO Packet Bytes Available Count (RPBA[6:0]). RPBA0 is the LSB.
PS2
0
0
0
0
1
0 = Bytes indicated by RPBA0 through RPBA6 are the end of a message. Host must check the HDLC-64
status register for details.
1 = Bytes indicated by RPBA0 through RPBA6 are the beginning or continuation of a message. The host
does not need to check the HDLC-64 status. The MS bit returns to a value of 1 when the Rx HDLC-64
FIFO is empty.
PS1
0
0
1
1
0
MS
—
7
0
7
0
PS0
0
1
0
1
0
In Progress: End of message has not yet been reached.
Packet OK: Packet ended with correct CRC codeword.
CRC Error: A closing flag was detected, preceded by a corrupt CRC codeword.
Abort: Packet ended because an abort signal was detected (7 or more ones in a row).
Overrun: HDLC-64 controller terminated reception of packet because receive FIFO is
full.
RRTS5
Receive Real-Time Status Register 5 (HDLC-64)
0B4h + (200h x (n - 1)) : where n = 1 to 8
RHPBA
Receive HDLC-64 Packet Bytes Available Register
0B5h + (200h x (n - 1)) : where n = 1 to 8
RPBA6
PS2
6
0
6
0
RPBA5
PS1
5
0
5
0
RPBA4
199 of 312
PS0
0
0
4
4
PACKET STATUS
RPBA3
—
3
0
3
0
RPBA2
—
2
0
2
0
RHWM
RPBA1
1
0
1
0
RPBA0
RNE
0
0
0
0