DS26518GNB1+ Maxim Integrated Products, DS26518GNB1+ Datasheet - Page 184

• Manufacturer Part Number: DS26518GNB1+
• Description: IC TXRX T1/E1/J1 8PRT 256-CSBGA
• Manufacturer: Maxim Integrated Products
• Type: Transceiverr

Specifications of DS26518GNB1+

• Number Of Drivers/receivers: 8/8
• Protocol: T1/E1/J1
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 256-CSBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Note: All bits in this register are latched and can create interrupts. See
Bit 5: Receive RAI-CI Detect (RRAI-CI). Set when an RAI-CI pattern has been detected by the receiver. This bit is
active in ESF framing mode only, and will set only if an RAI condition is being detected (RRTS1.3). When the host
reads (and clears) this bit, it will set again each time the RAI-CI pattern is detected (approximately every 1.1
seconds).
Bit 4: Receive AIS-CI Detect (RAIS-CI). Set when an AIS-CI pattern has been detected by the receiver. This bit
will set only if an AIS condition is being detected (RRTS1.2). This is a latched bit that must be cleared by the host,
and will set again each time the AIS-CI pattern is detected (approximately every 1.2 seconds).
Bit 3: Receive SLC-96 Alignment Event (RSLC96). Set when a valid SLC-96 alignment pattern is detected in the
Fs bit stream, and the T1RSLC1–3 registers have data available for retrieval. See Section
information.
Bit 2: Receive FDL Register Full Event (RFDLF). Set when the 8-bit
operation, or manual extraction of FDL data bits. See Section
Bit 1: BOC Clear Event (BC). Set when a valid BOC is no longer detected (with the disintegration filter applied).
Bit 0: BOC Detect Event (BD). Set when a valid BOC has been detected (with the BOC filter applied).
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Note: All bits in this register are latched and can create interrupts. See
Bit 1: Sa6 Codeword Detect (Sa6CD). Set when a valid codeword (per ETS 300 233) is detected in the Sa6 bit
positions.
Bit 0: SaX Bit Change Detect (SaXCD). Set when a bit change is detected in the SaX bit position. The enabled
SaX bits are selected by
—
—
7
0
7
0
theE1RSAIMR
RLS7 (T1 Mode)
Receive Latched Status Register 7
096h + (200h x (n - 1)) : where n = 1 to 8
RLS7 (E1 Mode)
Receive Latched Status Register 7
096h + (200h x (n - 1)) : where n = 1 to 8
—
—
6
0
6
0
RRAI-CI
register.
—
5
0
5
0
184 of 312
RAIS-CI
—
4
0
4
0
9.9.5.4
RLS7
RLS7
RSLC96
—
3
0
3
0
for more information.
for E1 Mode.
for T1 Mode.
T1RFDL
RFDLF
register is full. Useful for SLC-96
—
2
0
2
0
9.9.4.4
Sa6CD
BC
1
0
1
0
for more
SaXCD
BD
0
0
0
0