DS26518GNB1+ Maxim Integrated Products, DS26518GNB1+ Datasheet - Page 235
DS26518GNB1+
Manufacturer Part Number
DS26518GNB1+
Description
IC TXRX T1/E1/J1 8PRT 256-CSBGA
Manufacturer
Maxim Integrated Products
Type
Transceiverr
Datasheet
1.DS26518GNB1.pdf
(312 pages)
Specifications of DS26518GNB1+
Number Of Drivers/receivers
8/8
Protocol
T1/E1/J1
Voltage - Supply
3.135 V ~ 3.465 V
Mounting Type
Surface Mount
Package / Case
256-CSBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Note: All bits in this register are real time.
Bit 3: Transmit FIFO Empty (TEMPTY). A real-time bit that is set high when the FIFO is empty.
Bit 2: Transmit FIFO Full (TFULL). A real-time bit that is set high when the FIFO is full.
Bit 1: Transmit FIFO Below Low Watermark Condition (TLWM). Set when the transmit 64-byte FIFO empties
beyond the low watermark as defined by the transmit low watermark bits (TLWM).
Bit 0: Transmit FIFO Not Full Condition (TNF). Set when the transmit 64-byte FIFO has at least one byte
available.
Register Name:
Register Description:
Register Address:
Bit #
Name Name— TFBA6 TFBA5 TFBA4 TFBA3 TFBA2 TFBA1 TFBA0
Bits 6 to 0: Transmit FIFO Bytes Available (TFBA6 to TFBA0). TFBA0 is the LSB.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: Transmit HDLC-64 Data Bit 7 (THD7). MSB of an HDLC-64 packet data byte.
Bit 6: Transmit HDLC-64 Data Bit 6 (THD6)
Bit 5: Transmit HDLC-64 Data Bit 5 (THD5)
Bit 4: Transmit HDLC-64 Data Bit 4 (THD4)
Bit 3: Transmit HDLC-64 Data Bit 3 (THD3)
Bit 2: Transmit HDLC-64 Data Bit 2 (THD2)
Bit 1: Transmit HDLC-64 Data Bit 1 (THD1)
Bit 0: Transmit HDLC-64 Data Bit 0 (THD0). LSB of an HDLC-64 packet data byte.
THD7
—
7
0
7
7
0
TRTS2
Transmit Real-Time Status Register 2 (HDLC-64)
1B1h + (200h x (n - 1)) : where n = 1 to 8
TFBA
Transmit HDLC-64 FIFO Buffer Available Register
1B3h + (200h x (n - 1)) : where n = 1 to 8
THF
Transmit HDLC-64 FIFO Register
1B4h + (200h x (n - 1)) : where n = 1 to 8
THD6
—
6
0
6
6
0
THD5
—
5
0
5
5
0
235 of 312
THD4
—
0
0
4
4
4
TEMPTY
THD3
3
0
3
3
0
TFULL
THD2
Default 0 0 0 0 0 0 0 0
2
0
2
2
0
TLWM
THD1
1
0
1
1
0
THD0
TNF
0
0
0
0
0
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