DS26518GNB1+ Maxim Integrated Products, DS26518GNB1+ Datasheet - Page 2

• Manufacturer Part Number: DS26518GNB1+
• Description: IC TXRX T1/E1/J1 8PRT 256-CSBGA
• Manufacturer: Maxim Integrated Products
• Type: Transceiverr

Specifications of DS26518GNB1+

• Number Of Drivers/receivers: 8/8
• Protocol: T1/E1/J1
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 256-CSBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
8.1
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9
9.1.1
9.1.2
9.2.1
9.2.2
9.4.1
9.8.1
9.8.2
9.8.3
9.8.4
9.8.5
9.8.6
9.9.1
9.9.2
9.9.3
9.9.4
9.9.5
9.9.6
9.9.7
DETAILED DESCRIPTION.................................................................................................9
FEATURE HIGHLIGHTS ..................................................................................................10
APPLICATIONS ...............................................................................................................13
SPECIFICATIONS COMPLIANCE ...................................................................................14
ACRONYMS AND GLOSSARY .......................................................................................16
MAJOR OPERATING MODES.........................................................................................17
BLOCK DIAGRAMS.........................................................................................................18
PIN DESCRIPTIONS ........................................................................................................20
FUNCTIONAL DESCRIPTION .........................................................................................28
G
L
C
J
F
S
HDLC C
T
M
P
P
C
R
I
G
P
D
S
F
NITIALIZATION AND
ITTER
INE
RAMER
EST AND
RAMERS
YSTEM
IN
ROCESSOR
ER
YSTEM
LOCK
LOCK
ESETS AND
EVICE
ENERAL
LOBAL
ICROCONTROLLER
S
LAVE
F
SPI Serial Port Mode............................................................................................................................ 28
SPI Functional Timing Diagrams ......................................................................................................... 28
Backplane Clock Generation ............................................................................................................... 31
CLKO Output Clock Generation........................................................................................................... 32
Example Device Initialization and Sequence ....................................................................................... 34
-P
Elastic Stores ....................................................................................................................................... 36
IBO Multiplexing ................................................................................................................................... 39
H.100 (CT Bus) Compatibility .............................................................................................................. 45
Transmit and Receive Channel Blocking Registers............................................................................. 47
Transmit Fractional Support (Gapped Clock Mode) ............................................................................ 47
Receive Fractional Support (Gapped Clock Mode) ............................................................................. 47
T1 Framing........................................................................................................................................... 48
E1 Framing........................................................................................................................................... 51
T1 Transmit Synchronizer .................................................................................................................... 53
Signaling .............................................................................................................................................. 54
T1 Data Link......................................................................................................................................... 59
E1 Data Link......................................................................................................................................... 61
Maintenance and Alarms ..................................................................................................................... 62
I
UNCTIONAL
NTERFACE
ORT
A
S
S
I
/F
R
NTERRUPTS
I
ONTROLLERS
B
TTENUATOR
YNTHESIZERS
S
TRUCTURE
NTERFACE
......................................................................................................................................10
......................................................................................................................................48
D
ESOURCES
ACKPLANE
ORMATTER
ERIAL
R
IAGNOSTICS
ESOURCES
I
P
NTERFACE
OWER
............................................................................................................................10
P
D
ERIPHERAL
ESCRIPTION
C
.......................................................................................................................31
......................................................................................................................11
P
-D
.....................................................................................................................10
.....................................................................................................................34
ONFIGURATION
I
....................................................................................................................11
....................................................................................................................34
NTERFACE
ARALLEL
...................................................................................................................12
..................................................................................................................10
OWN
................................................................................................................12
................................................................................................................28
................................................................................................................34
M
I
NTERFACE
ODES
......................................................................................................20
TABLE OF CONTENTS
P
ORT
...................................................................................................36
..............................................................................................33
..............................................................................................34
.............................................................................................12
(SPI) F
2 of 312
EATURES
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