DS26518GNB1+ Maxim Integrated Products, DS26518GNB1+ Datasheet - Page 23

• Manufacturer Part Number: DS26518GNB1+
• Description: IC TXRX T1/E1/J1 8PRT 256-CSBGA
• Manufacturer: Maxim Integrated Products
• Type: Transceiverr

Specifications of DS26518GNB1+

• Number Of Drivers/receivers: 8/8
• Protocol: T1/E1/J1
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 256-CSBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RSYSCLK2/
RSYSCLK3/
RSYSCLK4/
RSYSCLK5/
RSYSCLK6/
RSYSCLK7/
RSYSCLK8/
RSYSCLK1
RLF/LTC2
RLF/LTC3
RLF/LTC4
RLF/LTC5
RLF/LTC6
RLF/LTC7
RLF/LTC8
RSYNC1
RSYNC2
RSYNC2
RSYNC2
RSYNC5
RSYNC6
RSYNC7
RSYNC8
RSER1
RSER2
RSER3
RSER4
RSER5
RSER6
RSER7
RSER8
RCLK1
RCLK2
RCLK3
RCLK4
RCLK5
RCLK6
RCLK7
RCLK8
NAME
M11
M12
M14
N14
D14
R10
C11
D13
B12
F11
K13
F13
E13
E14
P12
PIN
J13
L12
G4
M4
M3
E5
D6
N4
N6
E3
N3
A4
B6
N5
F4
L4
T6
Input with
pulldown/
internal
Output
Output
Output
Output
TYPE
Input/
Input
Received Serial Data 1 to 8. Received NRZ serial data. Updated on rising edges
of RCLKn when the receive-side elastic store is disabled. Updated on the rising
edges of RSYSCLKn when the receive-side elastic store is enabled.
When IBO mode is used, the RSERn pins can output data for multiple framers.
The RSERn data is synchronous to RSYSCLKn. See Section
9-6.
Receive Clock 1 to 8. A 1.544MHz (T1) or 2.048MHz (E1) clock that is used to
clock data through the receive-side framer. This clock is recovered from the
signal at RTIPn and RRINGn. RSERn data is output on the rising edge of RCLKn.
RCLKn is used to output RSERn when the elastic store is not enabled or IBO is
not used. When the elastic store is enabled or IBO is used, the RSERn is clocked
by RSYSCLKn.
Receive System Clock 1. 1.544MHz, 2.048MHz, 4.096MHz, 8.192MHz, or
16.384MHz receive backplane clock. Only used when the receive-side elastic
store function is enabled. Should be tied low in applications that do not use the
receive-side elastic store. Multiple of 2.048MHz is expected when the IBO mode
is used. Note: If the GTCR1.528MD bit is set, RSYSCLK1 becomes the master
RSYSCLK for all framers.
Receive System Clock 2 to 8. 1.544MHz, 2.048MHz, 4.096MHz, 8.192MHz, or
16.384MHz receive backplane clock. Only used when the receive-side elastic
store function is enabled. Should be tied low in applications that do not use the
receive-side elastic store. Multiple of 2.048MHz is expected when the IBO Mode
is used.
Receive Loss of Frame/Loss of Transmit Clock. This pin can also be
programmed to either toggle high when the synchronizer is searching for the
frame and multiframe or to toggle high if the TCLKn pin has not been toggled for
approximately three clock periods.
RLF/LTC[8:2] are available when GTCR1.528MD = 1.
Note: If the GTCR1.528MD bit is set, RSYSCLK1 becomes the master
RSYSCLK for all framers.
Receive Synchronization 1 to 8. If the receive-side elastic store is enabled, this
signal is used to input a frame or multiframe boundary pulse. If set to output
frame boundaries, RSYNCn can be programmed to output double-wide pulses on
signaling frames in T1 mode. In E1 mode, RSYNCn out can be used to indicate
CAS and CRC-4 multiframe. The DS26518 can accept an H.100-compatible
synchronization signal. The default direction of this pin at power-up is input, as
determined by the RSIO control bit in the RIOCR.2 register.
RECEIVE FRAMER
23 of 312
FUNCTION
9.8.2
and
Table