DS26518GNB1+ Maxim Integrated Products, DS26518GNB1+ Datasheet - Page 173

• Manufacturer Part Number: DS26518GNB1+
• Description: IC TXRX T1/E1/J1 8PRT 256-CSBGA
• Manufacturer: Maxim Integrated Products
• Type: Transceiverr

Specifications of DS26518GNB1+

• Number Of Drivers/receivers: 8/8
• Protocol: T1/E1/J1
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 256-CSBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: One-Second Select (1SECS). This bit allows for synchronization of the error counter updates between
multiple ports. When ERCNT.3 = 0, setting this bit (on a specific framer) will update the framer’s error counters on
the transition of the one-second timer from framer 1. Note that this bit should always be clear for framer 1.
Bit 6 : Manual Counter Update Select (MCUS). When manual update mode is enabled with EAMS, this bit can be
used to allow the incoming LATCH_CNT signal to latch all counters. Useful for synchronously latching counters of
multiple DS26518 cores located on the same die.
Bit 5: Manual Error Counter Update (MECU). When enabled by ERCNT.3, the changing of this bit from a 0 to a 1
allows the next clock cycle to load the error counter registers with the latest counts and reset the counters. The
user must wait a minimum of 250 μ s before reading the error count registers to allow for proper update.
Bit 4: Error Counter Update Select (ECUS)
Bit 3: Error Accumulation Mode Select (EAMS)
Bit 2: PCVCR Fs-Bit Error Report Enable (FSBE) (T1 Mode Only)
Bit 1: Multiframe Out of Sync Count Register Function Select (MOSCRF) (T1 Mode Only)
Bit 0: T1 Line Code Violation Count Register Function Select (LCVCRF)
0 = Use the one-second timer that is internal to the framer.
1 = Use the one-second timer from framer 1 to latch updates.
0 = MECU is used to manually latch counters.
1 = Counters are latched on the rising edge of the LATCH_CNT signal.
T1 mode:
0 = Update error counters once a second.
1 = Update error counters every 42ms (333 frames).
E1 mode:
0 = Update error counters once a second.
1 = Update error counters every 62.5ms (500 frames).
0 = Automatic updating of error counters enabled. The state of ERCNT.4 determines accumulation time
(timed update).
1 = User toggling of ERCNT.5 determines accumulation time (manual update).
0 = Do not report bit errors in Fs-bit position; only Ft-bit position.
1 = Report bit errors in Fs-bit position as well as Ft-bit position.
0 = Count errors in the framing bit position.
1 = Count the number of multiframes out of sync.
0 = Do not count excessive zeros.
1 = Count excessive zeros.
1SECS
1SECS
7
0
ERCNT
Error Counter Configuration Register
086h + (200h x (n - 1)) : where n = 1 to 8
MCUS
MCUS
6
0
MECU
MECU
5
0
173 of 312
ECUS
ECUS
0
4
EAMS
EAMS
3
0
FSBE
—
2
0
MOSCRF
—
1
0
LCVCRF
LCVCRF
0
0