BBT3821-JH Intersil, BBT3821-JH Datasheet - Page 74

• Manufacturer Part Number: BBT3821-JH
• Description: IC RE-TIMER OCTAL 192-BGA
• Manufacturer: Intersil
• Type: Clock and Data Recovery (CDR)r

Specifications of BBT3821-JH

• Input: Differential
• Output: CML
• Frequency - Max: 3.1875GHz
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 192-EBGA
• Frequency-max: 3.1875GHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

many TOSA, ROSA and lane-oriented DOM devices have
open-drain outputs that go high on an alarm condition, wire-
AND-ing these together for a four-lane indication is not
possible (any ‘working’ lane masks the ‘alarmed’ lane(s)),
some external gating may be required (typically a 4-input OR
or NOR gate per alarm). Note that the default polarity of
these alarm inputs (active high) will be set after power-up,
RESET or a hard (D.0.15) software reset, until the device is
reconfigured. If a host-driven configuration is being used, the
polarities (controlled by 1.C01D, Table 55) should be set
before the LASI enables (1.9002, Table 27). If the Auto-
Configure system is used (See “Auto-Configuring Control
Registers” on page 16 and Table 92), the configuration may
take typically about 100 msec (see Figure 18 and Table 117),
and there will normally be a brief interval during which the
LASI interrupt is likely to be (incorrectly) activated. LASI host
operations would probably normally ignore such ‘glitches’,
since the Byte Synch and Lane Alignment will initially be in
‘Fault’ condition after such a RESET (per the IEEE 802.3ae
specification), and so the relevant latched Local Fault
indications will need to be cleared before LASI is
meaningful, but it could be advisable to ensure that the
additional indications are ignored or cleared in the same way
before the full LASI system is activated.
TX_FAULT
OPRXOP
- - - etc. - - -
TX_ENA#
RAW_3V3
RAW_3V3
Rpd
12K
Rpu
74
Rpu
Rpd
10k
12K
16K
18K for
MIC3000
12K
Rpu
Rpd
10k
- - - etc.- - -
TX_FAULT_3P3
OPRXOP_3P3
TX_ENA3P3_#
FIGURE 26. RESISTIVE DIVIDER CIRCUITS
BBT3821
TX_FAULT
OPRXOP
- - - etc. - - -
SDA, SCL
10K
12K
R2
R3
- - - each- - -
Rpd
10K
RAW_3V3
FIGURE 25. V
Rpu
Rpd
LMV431
3
Rpd
10K
Reference
U1
12K
30K
From MSA Conn
Rpu
12K
Rpu
12K
SDA, SCL
Cathode
DDPR
Anode
1
2
- - - etc. - - -
R1
68
CLAMP CIRCUIT
TX_FAULT_3P3
OPRXOP_3P3
P3V3
Cathode
Anode
B
A
Pull-Up Resistors
To BBT3821,
ZHCS400
D1
VDDPR
VDD