BBT3821-JH Intersil, BBT3821-JH Datasheet - Page 52

• Manufacturer Part Number: BBT3821-JH
• Description: IC RE-TIMER OCTAL 192-BGA
• Manufacturer: Intersil
• Type: Clock and Data Recovery (CDR)r

Specifications of BBT3821-JH

• Input: Differential
• Output: CML
• Frequency - Max: 3.1875GHz
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 192-EBGA
• Frequency-max: 3.1875GHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Auto-configure Pointer is (S), Auto-configure Size is (N), from 1.8106’h & 1.8105’h respectively
Note (1): The 8 bits of the NVR register (7:0) are mapped to the listed bits of the target in order. Unused bits are always at the MSb (bit 7) end.
Note (2): The target register pair are overlapped, ignoring the ‘reserved’ bits in one where used bits occur in the same location in the other. Thus the mapping from the
Note (3): The mapping from the NVR register is: 1.C004.[11:8], 3.C004.[3:0]
S + 7
S + 8
S + 9
S + 10
S + 11
S + 12
S + 13
S + 14
S + 15
S + 16
S + 17
S + 18
S + 19
S + 20
S + 21
S + 22
S + 23
S + 24
S + 25
S + 26
S + 27
S + 28
S + 29
S + 30
S + 31
S + 32
S + 33
S + 34
S + 35
S + 36
S + 37
S + 38
S + 39
NVR ADDRESS
DEC
NVR register is: 1.C001.[15:12], 3.C001.11, 1.C001.[10:8].
S + 7
S + 8
S + 9
S + A
S + B
S + C
S + D
S + E
S + F
S + 10
S + 11
S + 12
S + 13
S + 14
S + 15
S + 16
S + 17
S + 18
S + 19
S + 1A
S + 1B
S + 1C
S + 1D
S + 1E
S + 1F
S + 20
S + 21
S + 22
S + 23
S + 24
S + 25
S + 26
S + 27
HEX
1.36865.[7:0]
1.36865.[10:8]
& 1.36866.[3:0]
1.36870.
1.36871.
1.49170.[1:0],
1.49168.[5:0]
1.49170.[11:8,5:2],
1.49170.[13:12],
1.49171.[5:0]
1.49176
1.49177.[7:0]
1.49177.[15:8]
1.49178.[7:0]
1.49178.[15:8]
1.49179.[7:0]
1.49179.[15:8]
1.49180.[7:0]
1.49180.[15:8]
1.49181.[7:0]
4.49152.[7:0]
4.49152.[15:8]
4.49153.[7:0]
4.49153.[15:8]
4.49154.[7:0]
4.49155.[7:0]
4.49156.[11:8,3:0]
3.49152.[7:0]
3.49152.[15:8]
3.49153.[7:0]
1:3.49153.[15:8]
3.49154.[7:0]
3.49155.[7:0]
1.49156.[11:8]
3.49156.[3:0]
1.49163.[9:2]
4.49163.[9:2]
TARGET REGISTER BITS ADDRESS
52
DEC
Table 92. AUTO-CONFIGURE REGISTERS (Continued)
1.9001.[7:0]
1.9001.[10:8],
1.9002.[3:0]
1.9006
1.9007
1.C012.[1:0],
1.C010.[5:0]
1.C012.[11:8,5:2]
1.C012.[13:12],
1.C013.[5:0]
1.C018
1.C019.[7:0]
1.C019.[15:8]
1.C01A.[7:0]
1.C01A.[15:8]
1.C01B.[7:0]
1.C01B.[15:8]
1.C01C.[7:0]
1.C01C.[15:8]
1.C01D.[7:0]
4.C000.[7:0]
4.C000.[15:8]
4.C001.[7:0]
4.C001.[15:8]
4.C002.[7:0]
4.C003.[7:0]
4.C004.[11:8,3:0]
3.C000.[7:0]
3.C000.[15:8]
3.C001.[7:0]
1:3.C001.[15:8]
3.C002.[7:0]
3.C003.[7:0]
1.C004.[11:8]
3.C004.[3:0]
1.C00B.[9:2]
4.C00B.[9:2]
HEX
BBT3821
(1)
LASI TX Alarm Control
LASI TX Alarm & LASI Control
DOM TX flag control
DOM RX flag control
GPIO LASI & Pin Direction Configuration
GPIO LASI control
TX_FAULT polarity, GPIO LASI & Output Control Table 49 &
DOM Control
Indirect DOM Mem Address Lane2
Indirect DOM Mem Address Lane3
Indirect DOM Mem Address Lane0
Indirect DOM Mem Address Lane1
Indirect DOM Dev Address Lane2
Indirect DOM Dev Address Lane3
Indirect DOM Dev Address Lane0
Indirect DOM Dev Address Lane1
Optical I/F Pin Polarity Control
PHY XS control 2
PHY XS control 2
PHY XS control 3
PHY XS control 3
PHY XS Error Code
PHY XS IDLE Code
PHY XS Loopback Control
PCS control 2
PCS control 2
PCS control 3
PCS control 3/PMA control 2
PCS Error Code
PCS IDLE Code
PCS/PMA Loopback Control
Miscellaneous Adjustments
BitBlitz Internal Test Control
TARGET NAME
(1)
Table 25
Table 25 &
Table 26
Table 30
Table 31
Table 49 &
Table 47
Table 49
Table 50
Table 51
Table 53
Table 54
Table 55
Table 80
Table 81
Table 82
Table 83
Table 85
Table 63
Table 64 &
Table 39
Table 66
Table 67
Table 40 &
Table 68
Table 45
Table 91
DETAILS
(2)
(3)