BBT3821-JH Intersil, BBT3821-JH Datasheet - Page 35

• Manufacturer Part Number: BBT3821-JH
• Description: IC RE-TIMER OCTAL 192-BGA
• Manufacturer: Intersil
• Type: Clock and Data Recovery (CDR)r

Specifications of BBT3821-JH

• Input: Differential
• Output: CML
• Frequency - Max: 3.1875GHz
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 192-EBGA
• Frequency-max: 3.1875GHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Note (1): Default values depend on setting of LX4/CX4 select LX4_MODE pin. LX4 value is shown first. The value may be overwritten by the Auto-Configure operation
Note (1): These bits are latched low on any SIG_DET failure condition detected. They are reset high on being read.
Note (2): These bits are latched high on any LOS condition detected. They are reset low on being read.
Note (1): Default values depend on setting of LX4/CX4 select LX4_MODE pin. LX4 value is shown first. The value may be overwritten by the Auto-Configure operation
Note (1): This reset will NOT cause a reload of the NVR or DOM areas, nor an Auto-Configure operation. It will reset the Byte Sync engine, the Lane Alignment engine,
1.49162.15:8
1.49162.7
1.49162.6
1.49162.5
1.49162.4
1.49162.3
1.49162.2
1.49162.1
1.49162.0
1.49158.15:14
1.49158.3:0
1.49163.15:10
1.49163.9:6
1.49163.5:2
1.49163.1:0
1.49167.15
[3,4].49167.15
[1,3:4].49167.14:0
BIT
(See “Auto-Configuring Control Registers” on page 16 and Table 92 for details).
(See “Auto-Configuring Control Registers” on page 16 and Table 92 for details).
the FIFO pointers, and the I
re-established, and any DOM update in progress may be aborted.
BIT
BIT
BIT
Reserved
SIG_DET_3
SIG_DET_2
SIG_DET_1
SIG_DET_0
PMA_LOS_3
PMA_LOS_2
PMA_LOS_1
PMA_LOS_0
Reserved
PMA EQ_COEFF
NAME
Pre-emphasis
Reserved
Amplitude
Reserved
SOFT_RESET
Reserved
NAME
35
2
C controller. The BBT3821 will (if “normally” configured) transmit ||LF|| local fault signals until Byte Sync and Lane Alignment are
NAME
NAME
Table 44. PMA SIG_DET AND LOS DETECTOR STATUS REGISTER
Table 45. PMA/PMD MISCELLANEOUS ADJUSTMENT REGISTER
Table 46. PMA/PMD/PCS/PHY XS SOFT RESET REGISTER
MDIO REGISTER ADDRESS = [1,3:4].49167 ([1,3:4].C00F’h)
1 = CX4 Signal Detect
Asserted
0 = CX4 Signal Detect
Deasserted
1 = Signal less than
threshold
0 = Signal greater than
threshold
0’h = no boost in
equalizer.
F’h = boost is maximum
MDIO REGISTER ADDRESS = 1.49162 (1.C00A’h)
MDIO REGISTER ADDRESS = 1.49163 (1.C00B’h)
MDIO REGISTER ADDRESS = 1.49158 (1.C006’h)
Table 43. PMA/PMD EQUALIZATION CONTROL
Output Control
Fine Control per
lane
Internal
Write 1 to initiate.
SETTING
SETTING
SETTING
SETTING
(1)
BBT3821
(1)
00’b
1’b
1’b
1’b
1’b
0’b
0’b
0’b
0’b
0’h/C’h
00’h
LX4: 5’h
CX4: 3’h
LX4: 0’h
CX4: F’h
00’b
0’b
DEFAULT
DEFAULT
DEFAULT
DEFAULT
(1)
RO/LL
RO/LH
(2)
R/W
R/W
R/W
R/W
R/W SC Reset the entire chip except MDIO register
R/W
R/W
R/W
R/W
(1)
Configuration of the PMA/PMD equalizer
Bit 5 is for Lane 3, etc.
Test Function, do not alter.
settings
Signal Detect for PMA lane 2
Signal Detect for PMA lane 1
Signal Detect for PMA lane 0
Signal Detect for PMA lane 3
Loss Of Signal for PMA lane 3
Loss Of Signal for PMA lane 2
Loss Of Signal for PMA lane 1
Loss Of Signal for PMA lane 0
(1)
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION