BBT3821-JH Intersil, BBT3821-JH Datasheet - Page 14

• Manufacturer Part Number: BBT3821-JH
• Description: IC RE-TIMER OCTAL 192-BGA
• Manufacturer: Intersil
• Type: Clock and Data Recovery (CDR)r

Specifications of BBT3821-JH

• Input: Differential
• Output: CML
• Frequency - Max: 3.1875GHz
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 192-EBGA
• Frequency-max: 3.1875GHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

PHY XS (Serial) Loopback (4.0.14 & 4.C004.[11:8])
The PHY XS loopback is implemented from the output of the
TXP[3:0] serializers to the input multiplexers in front of the
RXP[3:0] CDRs. All four lanes are controlled by bit 4.0.14,
while the individual lanes can be controlled (one at a time) by
the 4.C004’h.[11:8] bits. Assuming that this is the only
loopback enabled, and that the BIST and test pattern
generation features are not enabled, the signal flow is from
the RCX[3:0][P/N] pins through almost all the ‘ingress’
channel to the input of the (still active) TXP[3:0] output drivers,
then (bypassing the RXP[3:0][P/N] inputs, the equalizers and
LOS detectors) back from the CDRs through almost all the
‘egress’ channel to the TCX[3:0][P/N] pins.
PCS Parallel Network Loopback (3.C004.[3:0])
This loopback is implemented (at the internal XGMII-like level)
from the output of the RXFIFOs in the ‘ingress’ channel to the
input of the TXFIFOs in the ‘egress’ channel. The individual
lanes can be controlled (one at a time) by the 3.C004’h.[3:0]
bits. Assuming that this is the only loopback enabled, and that
the BIST and test pattern generation features are not enabled,
the signal flow is from the RCX[3:0][P/N] pins through the
PMA/PMD and PCS and again PMA/PMD to the
TCX[3:0][P/N] pins. This could also be seen as a ‘short’
loopback at the XGMII input of the PHY XS.
1.C001.10:8
1.C01D.6
OPRLOS
PMA/PMD
REG
REG
DETECT
SIGNAL
[3:0]
3.C001.10:8 level
REG
FIGURE 4. IEEE AND VENDOR SPECIFIC FAULT AND STATUS REGISTERS (EQUIVALENT SCHEMATIC)
1.C00A.7:4
SIGNAL_
DETECT
1.C00A.3:0
REG
CX4
ALIGN
SYNC
PHY XS
PHY XS
BYTE
LANE
REG
PCS
PCS
ALIGN
LANE
BYTE
SYNC
DETECT
PHY XS
SIGNAL
IEEE REG
IEEE REG
14
IEEE REG
IEEE REG
3.24.3:0
3.24.12
4.24.3:0
4.24.12
CX4
CX4
LX4
LX4
4.C00A.3:0
TXFAULT
1.C012h.13
POLARITY
REG
REG
IEEE REG
1.10.4:1
IEEE REG
1.1.2
PLL LOCK
BBT3821
FAIL
IEEE REG
See LASI
1.10.0
PCS (Parallel) Loopback (4.C004.[3:0] & Optionally
3.0.14)
This loopback is implemented (at the internal XGMII-like level)
from the output of the RXFIFOs in the ‘egress’ channel to the
input of the TXFIFOs in the ‘ingress’ channel. The individual
lanes can be controlled (one at a time) by the 4.C004’h.[3:0]
bits. If the enable bit in 3.C001.7 (Table 64) is set, all four
lanes can be controlled by bit 3.0.14. Since the latter is
specifically excluded by subclause 45.2.3.1.2 of the IEEE
802.3ae-2002 specification for a 10GBASE-X PCS, the
default is to NOT enable this loopback bit, and if it is enabled,
the BBT3821 does not conform to the IEEE specification. A
maintenance request has been submitted to the IEEE to
enable this loopback bit as optional, and to allow a ‘PCS
Loopback Capability’ bit in register bit 3.24.10 (see
http://www.ieee802.org/3/maint/requests/maint_1113.pdf), but
this has so far been rejected, and may never be approved.
Assuming that this is the only loopback enabled, and that the
BIST and test pattern generation features are not enabled, the
signal flow is from the RXP[3:0][P/N] pins through the full PHY
XS via the internal XGMII to the TXP[3:0][P/N] pins. This
could also be seen as a ‘short’ loopback at the XGMII input of
the PCS.
See LASI
IEEE REG
IEEE REG
3.1.2
4.1.2
IEEE REG
IEEE REG
IEEE REG
IEEE REG
IEEE REG
IEEE REG
3.8.10
4.8.10
1.8.11
1.8.10
3.8.11
4.8.11
See LASI
See LASI
See LASI
See LASI
See LASI
See LASI
IEEE REG
IEEE REG
IEEE REG
1.1.7
3.1.7
4.1.7