BBT3821-JH Intersil, BBT3821-JH Datasheet - Page 45

• Manufacturer Part Number: BBT3821-JH
• Description: IC RE-TIMER OCTAL 192-BGA
• Manufacturer: Intersil
• Type: Clock and Data Recovery (CDR)r

Specifications of BBT3821-JH

• Input: Differential
• Output: CML
• Frequency - Max: 3.1875GHz
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 192-EBGA
• Frequency-max: 3.1875GHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Note (1): The counters do not rollover at FF’h, and are cleared on read. There is also an error flag bit, see register 4.C007, Table 88.
Note (1): ‘V’ is a version number. See “JTAG & AC-JTAG Operations” on page 53 for a note about the version number.
Note (2): For rows with “A”, the default value may be overwritten by the Auto-Configure operation (See “Auto-Configuring Control Registers” on page 16 and Table 92
Note (3): Read value depends on status signal values. Value shown indicates ‘normal’ operation.
Note (4): The IEEE 802.3ae spec allows this to be all zeroes. A XENPAK (etc.) host can more readily determine where the NVR registers are if this value is zero.
3.49165.15:8
3.49165.7:0
3.49166.15:8
3.49166.7:0
4.0
4.1
4.2:3
4.4
4.5
4.6
4.8
4.14:15
4.24
4.25
4.49152
4.49153
4.49154
4.49155
4.49156
4.49157
4.49158
4.49159
4.49160
4.49161
4.49162
4.49163
4.49167
DEC
ADDRESS
for details).
BIT
4.0
4.1
4.2:3
4.4
4.5
4.6
4.8
4.E:F
4.18
4.19
4.C000
4.C001
4.C002
4.C003
4.C004
4.C005
4.C006
4.C007
4.C008
4.C009
4.C00A
4.C00B
4.C00F
HEX
BIST_ERR_CNT_3
BIST_ERR_CNT_2
BIST_ERR_CNT_1
BIST_ERR_CNT_0
PHYXS Control 1
PHYXS Status 1
ID Code
Speed Ability
IEEE Devices
Vendor Devices
PHYXS Status 2
Package ID
PHYXS Status 3
PHYXS Test
PHYXS Control 2
PHYXS Control 3
PHYXS ERR
PHYXS IDLE
PHYXS Loop Back PHY XS Loop Back Control Register
PRE_EMPH
Equalization
Test_Flags
Output Ctrl
Half Rate
LOS Det
Reserved
Soft Reset
NAME
45
NAME
MDIO REGISTER ADDRESSES = 3.49165:6 (3.C00D:E’h)
Reset, Enable loop back mode.
PCS Fault, Link Status
Manufacturer and Device OUI
10Gbps Ability
Devices in Package, Clause 22 capable
Vendor Specific Devices in Pkg
Device Present, Local Fault, Type Summary 8000’h
Package OUI, etc.
10GBASE-X PHY XGXS Status
10GBASE PHY XS Test Control
PHY XS Control Register 2
PHY XS Control Register 3
PHY XS Internal ERROR code register
PHY XS Internal IDLE Code Register
PHY XS Pre-emphasis level
PHY XS Equalization Control
PHY XS Receive Path Test & Status Flags
Output Control and Test function
Half rate clock mode enable
PHY XS Status 4 LOS Register
PHY XS Control 4 TXCLK20
Reset (non MDIO)
Table 73. BIST ERROR COUNTER REGISTERS
Table 74. MDIO PHY XS DEVAD 4 REGISTERS
Lane 3 errors
Lane 2 errors
Lane 1 errors
Lane 0 errors
PHY XS DEVICE 4 MDIO REGISTERS
SETTING
DESCRIPTION
BBT3821
00’h
00’h
00’h
00’h
DEFAULT
RCNR
RCNR
RCNR
RCNR
2040’h
0004’h
01839C6V’h
0001’h
001A’h
0000’h
00000000’h
1C0F’h
0000’h
0F6F’h
0800’h
00FE’h
0007’h
0000’h
0000’h
0000’h
0000’h
AAAA’h
0000’h
0000’h
0000’h
0000’h
R/W
DEFAULT
(1)
(1)
(1)
(1)
(3)
(3)
Error byte counter of BIST pattern
checker on each Lane
A
A
A
A
A
A
A
AC
(2)
R/W
RO
RO
RO
RO
R/W
R/W
R/W
R/W
RO (LL)
RO
RO
RO
R/W
R/W
R/W
R/W
R/W
R/W
RO LH
R/W
RO LH
R/W SC
DESCRIPTION
R/W
Table 75
See
Table 8
Table 8
See
Table 78
Table 81
Table 87
Table 89
Table 71
Table 91
Table 46
Table 76
Table 7
Table 77
Table 79
Table 80
Table 82
Table 83
Table 84
Table 85
Table 88
Table 90
DETAILS
(1)
(4)