BBT3821-JH Intersil, BBT3821-JH Datasheet - Page 47

• Manufacturer Part Number: BBT3821-JH
• Description: IC RE-TIMER OCTAL 192-BGA
• Manufacturer: Intersil
• Type: Clock and Data Recovery (CDR)r

Specifications of BBT3821-JH

• Input: Differential
• Output: CML
• Frequency - Max: 3.1875GHz
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 192-EBGA
• Frequency-max: 3.1875GHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Note (1): The status of these bits depends on the signal conditions. Default shown is for normal operation. The bits contribute to the RX Local Fault bit, see Table 77.
VENDOR-SPECIFIC PHY XS REGISTERS (4.C000’H TO 4.C00B’H)
4.24.15:13
4.24.12
4.24.11
4.24.10
4.24.9:4
4.24.3
4.24.2
4.24.1
4.24.0
4.25.15:3
4.25.2
4.25.1:0
4.49152.15:14
4.49152.13:12
4.49152.11
4.49152.10
4.49152.9:8
4.49152.7
4.49152.6:5
BIT
BIT
BIT
Reserved
PHY XS
TestPatEn
PHY XS TestPat
Type
Reserved
PHY XS
Lane_Align
Test_Pattern
PHYXSLpbk
Reserved
Lane3 Sync
Lane2 Sync
Lane1 Sync
Lane0 Sync
Test Mode
Reserved
PHY XS Clock
PSYNC
PHY XS CODECENA 0 = disable
PHY XS CDET[1:0]
PHY XS
DSKW_SM_EN
PHY XS RCLKMODE 11’b = Local
NAME
NAME
NAME
47
Receive Test Pattern
Enable
Test pattern select (see
Table 72 for other test
patterns generated by
the BBT3821)
Table 79. IEEE 10GBASE-X PHY XGXS TEST CONTROL REGISTER
1 = 4 Lanes Aligned
0 = Lanes not aligned
Test Pattern Abilities
Loopback Ability
1 = Lane is Synchronized
0 = Lane not Synchronized
Table 78. IEEE 10GBASE-X PHY XGXS STATUS REGISTER
SETTING
00’b
1 = enable
Comma Detect
Select.
0 = disable
1 = enable
Reference
Clock
SETTING
MDIO REGISTER ADDRESS = 4.49152 (4.C000’h)
MDIO REGISTER ADDRESSES = 4.24 (4.0018’h)
(4)
MDIO REGISTER ADDRESS = 4.25 (4.0019’h)
SETTING
Table 80. PHY XS CONTROL REGISTER 2
(2)
0’b
00’b
DEFAULT
00’b
1’b
1’b
11’b
0’b
11’b
DEFAULT
BBT3821
1’b
1’b
1’b
1’b
1’b
1’b
1’b
(1)
DEFAULT
R/W
R/W
(1)
(1)
(1)
(1)
(1)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0 = Do not enable Receive test pattern
1 = Enable Receive test pattern
11 = Reserved
10 = Mixed frequency test pattern (Continuous /K/ = K28.5)
01 = Low frequency test pattern (repeat 0000011111 = K28.7)
00 = High frequency test pattern (repeat 0101010101 = D10.2)
RO
RO
RO
RO
RO
RO
RO
User should leave at 00’b
1 = Synchronize/align four lanes
0 = Do not synchronize/align four lanes
Internal 8B/10B Codec enable/disable
These bits individually enable positive and negative disparity
“comma” detection.
11 = Enable both positive and negative comma detection
10 = Enable positive comma detection only
01 = Enable negative comma detection only
00 = Disable comma detection
Enable De-skew state machine control
by PHY XS XAUI_EN. May not operate correctly unless the
PHY XS PCS_SYNC_EN bit is also set.
Other values should only be used if incoming data is
frequency-synchronous with the local reference clock
R/W
1 = Device is able to loopback
1 = Four 3G receive lanes (on egress path) are
aligned
1 = The device is able to generate test patterns for
10GBASE-X
Reflects the PCS_SYNC byte alignment state
machine condition; not valid if not enabled in
device (see Table 80)
DESCRIPTION
DESCRIPTION
DESCRIPTION
(3)
. Forced enabled
(4)
.