BBT3821-JH Intersil, BBT3821-JH Datasheet - Page 28

• Manufacturer Part Number: BBT3821-JH
• Description: IC RE-TIMER OCTAL 192-BGA
• Manufacturer: Intersil
• Type: Clock and Data Recovery (CDR)r

Specifications of BBT3821-JH

• Input: Differential
• Output: CML
• Frequency - Max: 3.1875GHz
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 192-EBGA
• Frequency-max: 3.1875GHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Note (1): Where two descriptions are given, depends on LX4/CX4 select LX4_MODE pin. First value is LX4 value
Note (2): These mirrored bits will be cleared on a read of either this register or of their respective mirroring registers.
Note (3): This bit is derived from the OR of the LOS bits (1.C00A.3:0). In the case of a signal which is close to the LOS threshold value, so that LOS is changing over
Note (1): Where two descriptions are given, depends on LX4/CX4 select LX4_MODE pin. First value is LX4 value
Note (2): These mirrored bits will be cleared on read of either this register or their respective registers.
1.36867.15:6
1.36867.6
1.36867.5
1.36867.4
1.36867.3
1.36867.2
1.36867.1
1.36867.0
1.36868.15:11
1.36868.10
1.36868.9
1.36868.8
1.36868.7
1.36868.6
1.36868.5
1.36868.4
1.36868.3
1.36868.2
1.36868.1
1.36868.0
BIT
time for one or more lanes, this bit may give a “FAIL” indication even though the SIGNAL_DETECT function declares the signal “GOOD”, and Byte Synch and
Lane Align all indicate a “GOOD” signal.
BIT
Reserved
PCS Byte Synch
RX Receive
Power/Level
PMA LF
PCS LF
PCS Code
DOM RXFlg/
RX EFIFO
PHY RX LF
Reserved
PHY S_D
LBC
LTEMP
LOP
TX LF
Byte Sync
PMA LF
PCS LF
TX EFIFO
DOM TX/
PHY Code
PHY TX LF
NAME
NAME
28
1 = Alarm Condition is
Detected
0 = No Alarm Condition
is Detected
1 = Alarm Condition is
Detected
0 = No Alarm
Condition is Detected
Table 27. XENPAK LASI RX_ALARM STATUS REGISTER
Table 28. XENPAK LASI TX_ALARM STATUS REGISTER
SETTING
MDIO REGISTER, ADDRESS = 1.36867 (1.9003’h)
MDIO REGISTER, ADDRESS = 1.36868 (1.9004’h)
SETTING
000’h
0’b
0’b
0’b
0’b
0’b
0’b
0’b
0’b
0’b
0’b
0’b
BBT3821
000’h
0’b
0’b
0’b
0’b
0’b
DEFAULT
0’b
0’b
DEFAULT
RO/LH
RO/LH
RO/LH
RO/LH
RO/LH
RO/LH
RO/LH
RO/ LH
RO LH
RO LH
RO LH
RO LH
RO LH
RO LH
RO LH
RO LH
RO LH
RO LH
R/W
R/W
PCS Byte Sync Fail (logical NAND of bits 3.24.[3:0])
LX4: Receive Laser Power from OPRXOP pin (for
polarity see 1.49181)
CX4: Loss of Signal Detect
PMA/PMD RX Local Fault: mirror to bit 1.8.10
PCS RX Local Fault: mirror to bit 3.8.10
PCS 8b/10b Code Violation in any lane of PCS
LX4: DOM RX_Flag (from polling)
CX4: RX EFIFO over/underflow Fault
PHY RX Local Fault Status: mirror to bit 4.8.10
LX4: No fail detected
CX4: PHY XS Signal Detect Fail (XAUI)
LX4: Laser Bias Current Fault (from OPTXLBC pin, for
polarity see 1.49181)
CX4: No failure detectable
LX4: Laser Temperature Fault (from OPTTEMP pin, for
polarity see 1.49181)
CX4: No failure detectable
LX4: Laser Output Power Fault (from OPTXLOP pin, for
polarity see 1.49181)
CX4: No failure detectable
Transmit Local Fault (from TX_FAULT pin, for polarity
see 1.49170)
LX4: No fail detected
CX4: PHY XS Byte Sync Fail Status
PMA TX Local Fault Status: mirror to bit 1.8.11
LX4: PCS TX Local Fault Status: mirror to bit 3.8.11
CX4: No failure detectable
LX4: No fail detected
CX4: Transmit EFIFO Error Status
LX4: DOM TX_Flag (from polling)
CX4: PHY XS 8b/10b Code Violation
PHY TX Local Fault Status: mirror to bit 4.8.11
DESCRIPTION
DESCRIPTION
(3)
(1)
(1)
(2)
(2)
(2)
(2)
(2)
(2)