BBT3821-JH Intersil, BBT3821-JH Datasheet - Page 34

• Manufacturer Part Number: BBT3821-JH
• Description: IC RE-TIMER OCTAL 192-BGA
• Manufacturer: Intersil
• Type: Clock and Data Recovery (CDR)r

Specifications of BBT3821-JH

• Input: Differential
• Output: CML
• Frequency - Max: 3.1875GHz
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 192-EBGA
• Frequency-max: 3.1875GHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Note (1): Loopback is from Serial I/P to Serial O/P. Recommended use for test purposes only; the lanes are swapped, and no pre-emphasis is performed.
Note (2): These values may be overwritten by the Auto-Configure operation (See “Auto-Configuring Control Registers” on page 16 and Table 92 for details).
Note (1): Default values depend on setting of LX4/CX4 select LX4_MODE pin. LX4 value is shown firs
Note (1): See Figure 3 for illustration of the pre-emphasized waveform and meaning of symbols.
Note (2): This equation is the one used by the IEEE 802.3 CX4 Working Group when discussing pre-emphasis (alias Transmit equalization). The template normalization
Note (3): This is the Default value set on power-up or RESET if the LX4/CX4 LX4_MODE pin is set for CX4 operation. This setting allows for a small loss in the PCB
1.49156.15:13
1.49156.12
1.49156.11
1.49156.10
1.49156.9
1.49156.8
1.49156.7:0
1.49157.15:12
1.49157.11:8
1.49157.7:4
1.49157.3:0
ADDRESS
1.C005’h
BITS 3:0
0000
0001
0010
0100
0101
0111
0011
0110
(See “Auto-Configuring Control Registers” on page 16 and Table 92 for details).
factor of 0.69 in step 6) of IEEE 802.3akD5.3 Section 54.6.3.6 reflects 0.31 (31%) pre-emphasis according to this equation.
traces and connectors before the IEEE 802.3akD5.3 defined TP2 compliance measurement point. The value may be overwritten by the Auto-Configure
operation (See “Auto-Configuring Control Registers” on page 16 and Table 92 for details).
BIT
BIT
(3)
Reserved
PMA Test LP
PMA SLP_3
PMA SLP_2
PMA SLP_1
PMA SLP_0
Reserved
PRE-EMPHASIS
(802.3ak)
PRE_EMP Lane 3
PRE_EMP Lane 2
PRE_EMP Lane 1
PRE_EMP Lane 0
(1-V
14.0%
18.5%
22.0%
26.5%
30.0%
LOW
5.0%
9.5%
0%
NAME
34
/V
(2)
NAME
HI
=
)
Table 40. PMA SERIAL LOOP BACK CONTROL REGISTER
Table 42. PMA PRE-EMPHASIS CONTROL SETTINGS
MDIO REGISTER ADDRESS = 1.49157 (1.C005’h)
MDIO REGISTER ADDRESS = 1.49156 (1.C004’h)
1 = enable
0 = disable
PRE-EMPHASIS
Table 41. PMA PRE-EMPHASIS CONTROL
(V
SETTING
HI
VALUE =
See Table 42 for
settings
/ V
0.053
0.105
0.163
0.227
0.282
0.361
0.429
0
LOW
SETTING
)-1
BBT3821
0’h
0’b
0’b
0’b
0’b
DEFAULT
(1)
(1)
(2)
(2)
(2)
(2)
00’h/07’h
00’h/07’h
00’h/07’h
00’h/07’h
DEFAULT
ADDRESS
1.C005’h
BITS 3:0
1000
1001
1010
1011
1100
1101
1110
1111
R/W
R/W
R/W
(1)
t.
The values may be overwritten by the Auto-Configure operation
R/W
R/W
R/W
R/W
R/W
Serial Network Test Loopback
PMA Serial Loop Back Enable for each individual
lane. When high, it routes the internal PMA Serial
output to the PMA Serial input.
PRE-EMPHASIS
(802.3ak)
(1-V
33.0%
36.5%
40.0%
43.0%
46.0%
49.0%
52.0%
54.5%
Configure the level of PMA pre-emphasis
LOW
/V
(2)
HI
DESCRIPTION
=
)
DESCRIPTION
PRE-EMPHASIS
(V
HI
VALUE =
/ V
0.493
0.575
0.667
0.754
0.852
0.961
1.083
1.198
LOW
)-1