BBT3821-JH Intersil, BBT3821-JH Datasheet - Page 43

• Manufacturer Part Number: BBT3821-JH
• Description: IC RE-TIMER OCTAL 192-BGA
• Manufacturer: Intersil
• Type: Clock and Data Recovery (CDR)r

Specifications of BBT3821-JH

• Input: Differential
• Output: CML
• Frequency - Max: 3.1875GHz
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 192-EBGA
• Frequency-max: 3.1875GHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Note (1): The default value may be overwritten by the Auto-Configure operation (See “Auto-Configuring Control Registers” on page 16 and Table 92 for details).
Note (2): Equivalent to a loopback at the XGMII input side of the PHY XS.
Note (1): Note (1): These bits are latched high on any Fault condition detected. They are reset low (cleared) on being read. They will also be reset low on reading the
3.49156.15:4
3.49156.3
3.49156.2
3.49156.1
3.49156.0
3.49159.15:12
3.49159.11
3.49159.10
3.49159.9
3.49159.8
3.49159.7
3.49159.6
3.49159.5
3.49159.4
3.49159.3:0
3.49160.15:14
3.49160.13
3.49160.12:10
3.49160.9
3.49160.8:6
3.49160.5
3.49160.12:10
3.49160.1
3.49160.0
LASI register 1.9003’h (see Table 27)
BIT
BIT
BIT
Reserved
PLP_3
PLP_2
PLP_1
PLP_0
Test Flags
EFIFO_3
EFIFO_2
EFIFO_1
EFIFO_0
Code_3
Code_2
Code_1
Code_0
Test Flags
Reserved
ENA_3
Reserved
ENA_2
Reserved
ENA_1
Reserved
ENA_0
Reserved
NAME
NAME
NAME
43
Table 68. PCS PARALLEL NETWORK LOOP BACK CONTROL REGISTER
Table 70. PMA/PCS OUTPUT CONTROL & TEST FUNCTION REGISTER
1 = enable PCS Parallel
Network loopback
0 = disable
Table 69. PCS RECEIVE PATH TEST AND STATUS FLAGS
1 = EFIFO error in Lane
0 = no EFIFO error in
Lane
1 = 10b/8b Code error in
Lane
0 = no 10b/8b Code error
Enable Lane 3 O/P
Enable Lane 2 O/P
Enable Lane 1 O/P
Enable Lane 0 O/P
MDIO REGISTER ADDRESS = 3.49156 (3.C004’h)
MDIO REGISTER ADDRESS = 3.49159 (3.C007’h)
MDIO REGISTER ADDRESS = 3.49160 (3.C008’h)
SETTING
SETTING
SETTING
(2)
BBT3821
0’b
0’b
0’b
0’b
DEFAULT
(1)
(1)
(1)
(1)
0’h
0’b
0’b
0’b
0’b
0’b
0’b
0’b
0’b
0’h
DEFAULT
10’b
1’b
010’b
1’b
010’b
1’b
010’b
1’b
0’b
DEFAULT
R/W
R/W
ROLH
ROLH
ROLH
ROLH
ROLH
ROLH
ROLH
ROLH
ROLH
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PCS Parallel Network Loop Back Enable for each
individual lane. When high, routes the CX4/LX4 Serial
input to the CX4/LX4 Serial output via the XGMII side
of the PCS.
R/W
Special test use only
PCS Elasticity FIFO Overflow/Underflow Error
Detection
PCS 10b/8b Decoder Code Violation Detection
Special test use only
Test Function, do not alter
0 = disable (indep. of LX4_MODE)
Test Function, do not alter
0 = disable (indep. of LX4_MODE)
Test Function, do not alter
0 = disable (indep. of LX4_MODE)
Test Function, do not alter
0 = disable (indep. of LX4_MODE)
Test Function, do not alter
(1)
DESCRIPTION
DESCRIPTION
DESCRIPTION
(1)