BBT3821-JH Intersil, BBT3821-JH Datasheet - Page 27

• Manufacturer Part Number: BBT3821-JH
• Description: IC RE-TIMER OCTAL 192-BGA
• Manufacturer: Intersil
• Type: Clock and Data Recovery (CDR)r

Specifications of BBT3821-JH

• Input: Differential
• Output: CML
• Frequency - Max: 3.1875GHz
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 192-EBGA
• Frequency-max: 3.1875GHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

XENPAK LASI AND DOM REGISTERS (1.9000’H TO 1.9007’H & 1.A000’H TO 1.A100’H)
Note (1): Where two values are given, Default depends on LX4/CX4 select LX4_MODE pin. First value is LX4 value. The value may be overwritten by the Auto-
Note (1): Where two values are given, Default depends on LX4/CX4 select LX4_MODE pin. First value is LX4 value. The value may be overwritten by the Auto-
Note (1): The default values may be overwritten by the Auto-Configure operation (See “Auto-Configuring Control Registers” on page 16 and Table 92 for details). Since
Note (2): See description of the General Purpose Input/Output (GPIO) pins and bits for a description of how they contribute to the LASI system.
1.36864.15:7
1.36864.6
1.36864.5
1.36864.4
1.36864.3
1.36864.2
1.36864.1
1.36864.0
1.36865.15:11
1.36865.10
1.36865.9
1.36865.8
1.36865.7
1.36865.6
1.36865.5
1.36865.4
1.36865.3
1.36865.2
1.36865.1
1.36865.0
1.36866.15:4
1.36866.3
1.36866.2
1.36866.1
1.36866.0
BIT
Configure operation (See “Auto-Configuring Control Registers” on page 16 and Table 92 for details).
Configure operation (See “Auto-Configuring Control Registers” on page 16 and Table 92 for details).
on Power up or RESET several LASI contributors will initially be in the ‘fault’ condition (in particular, Byte Synch and Lane Alignment, and their derivatives), it
may be advisable for a host to clear these before enabling these to trigger LASI.
BIT
BIT
Reserved
RX Power
PCS LF
PCS Code
PHY RX LF
PCS Byte S
PMA LF
DOM RX
Reserved
PHY S_D
LBC
LTEMP
LOP
TX LF
Byte Sync
PMA LF
PCS LF
TX EFIFO
DOM TX/
PHY Code
PHY TX LF
Reserved
GPIO
RX_Alarm
TX_Alarm
LS_Alarm
NAME
NAME
NAME
27
1 = trigger LASI by
corresponding bit of
1.36867 (1.9003’h)
0 = LASI ignores
corresponding bit of
1.36867 (1.9003’h)
1 = trigger LASI from
corresponding bit of
1.36868 (1.9004’h)
0 = LASI ignores
corresponding bit of
1.36868 (1.9004’h)
1 = trigger LASI via bit in
1.36869 (1.9005’h)
0 = LASI ignores bit
Table 24. XENPAK LASI RX_ALARM CONTROL REGISTER
Table 25. XENPAK LASI TX_ALARM CONTROL REGISTER
SETTING
SETTING
MDIO REGISTER, ADDRESS = 1.36864 (1.9000’h)
MDIO REGISTER, ADDRESS = 1.36865 (1.9001’h)
MDIO REGISTER, ADDRESS = 1.36866 (1.9002’h)
Table 26. XENPAK LASI CONTROL REGISTER
SETTING
1’b/0’b
000’h
0’b/1’b
1’b/0’b
1’b/0’b
1’b/0’b
0’b/1’b
1’b
1’b/0’b
0’b/1’b
1’b
1’b
DEFAULT
000’h
0’b
1’b
1’b
1’b
0’b/1’b
1’b
1’b
DEFAULT
BBT3821
000’h
0’b
0’b
0’b
0’b
DEFAULT
(1)
(1)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
(1)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PHY XS Signal Detect LASI Enable
Laser Bias Current Fault LASI Enable
Laser Temperature Fault LASI Enable
Laser Output Power Fault LASI Enable
Transmit Local Fault LASI Enable
PHY XS Byte Sync Fail LASI Enable
PMA TX Local Fault LASI Enable
PCS TX Local Fault LASI Enable
Transmit EFIFO Error LASI Enable
DOM TX or PHY XS 8b/10b Code Violation Fault LASI
Enable
PHY TX Local Fault LASI Enable
PCS Byte Sync Fail LASI Enable
Receive Laser Pwr/Sig Det LASI Enable
PMA RX Local Fault LASI Enable
PCS RX Local Fault LASI Enable
8b/10b Code Violation LASI Enable
DOM RX or RX EFIFO Fault LASI Enable
PHY RX Local Fault LASI Enable
Enable GPIO pins to trigger LASI
Enable RX_Alarm to trigger LASI
Enable TX_Alarm to trigger LASI
Enable Link Status change to trigger LASI
DESCRIPTION
DESCRIPTION
DESCRIPTION
(2)