BBT3821-JH Intersil, BBT3821-JH Datasheet - Page 41

• Manufacturer Part Number: BBT3821-JH
• Description: IC RE-TIMER OCTAL 192-BGA
• Manufacturer: Intersil
• Type: Clock and Data Recovery (CDR)r

Specifications of BBT3821-JH

• Input: Differential
• Output: CML
• Frequency - Max: 3.1875GHz
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 192-EBGA
• Frequency-max: 3.1875GHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

VENDOR-SPECIFIC PCS REGISTERS (3.C000’H TO 3.C00E’H)
Note (1): The default values may be overwritten by the Auto-Configure operation (See “Auto-Configuring Control Registers” on page 16 and Table 92 for details).
Note (2): These bits are overridden by PCS XAUI_EN, see Table 64 and Table 65.
Note (3): These state machines are implemented according to 802.3ae-2002 clause 48.6.2.
Note (4): If the RCLKMODE bits are set to 10’b, the internal XGMII clock from the PCS to the PHY XS is set to the recovered clock. If the PCS Clock PSYNC bit is set
3.49152.15:14
3.49152.13:12
3.49152.11
3.49152.10
3.49152.9:8
3.49152.7
3.49152.6:5
3.49152.4
3.49152.3
3.49152.2
3.49152.1
3.49152.0
3.49153.15:12
3.49153.11
3.49153.10:8
3.49153.7
BIT
BIT
(the default), the recovered clock from Lane 0 is used for all four lanes, if cleared, or if the RCLKMODE bits are set to 01’b or 00’b, each lane uses its own
recovered clock. If the incoming data is NOT frequency-synchronous with the local reference clock, data will be corrupted (occasional characters will be lost,
or repeated).
Reserved
PCS XAUI_EN
Reserved
EN_PCSLB_EN
Test Mode
Reserved
PCS Clock PSYNC
PCS CODECENA
PCS CDET[1:0]
PCS
DSKW_SM_EN
PCS RCLKMODE
PCS_SYNC_EN
PCS IDLE_D_EN
PCS ELST_EN
PCS
A_ALIGN_DIS
PCS
CAL_EN
NAME
NAME
41
(4)
1 = enabled
1 = enabled
00’b
0 = disable
1 = enable
Comma Detect
Select
0 = disable
1 = enable
11’b = Local
Reference Clock
0 = disable
1 = enable
0 = disabled
0 = disabled
1 = disabled
0 = enabled
1 = enabled
0 = disabled
MDIO REGISTER ADDRESS = 3.49152 (3.C000’h)
MDIO REGISTER ADDRESS = 3.49153 (3.C001’h)
1 = enable
0 = disable
SETTING
Table 63. PCS CONTROL REGISTER 2
Table 64. PCS CONTROL REGISTER 3
SETTING
(2)
(2)
(1)
DEFAULT
00’b
1’b
1’b
11’b
0’b
11’b
0’b
1’b
1’b
1’b
1’b
BBT3821
DEFAULT
1’b
0’b
(1)
(1)
(1)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
User should leave at 00’b
1 = Synchronize/align four lanes
0 = Do not synchronize/align four lanes
Internal 8B/10B PCS Codec enable/disable
These bits individually enable positive and negative
disparity “comma” detection.
11 = Enable both positive and negative comma detection
10 = Enable positive comma detection only
01 = Enable negative comma detection only
00 = Disable comma detection
Enable De-skew state machine control
by XAUI_EN. May not operate correctly unless the
PCS_SYNC_EN bit is also set.
Other values should only be used if incoming data is
frequency-synchronous with the local reference clock
Enable 8b/10b PCS coding synchronized state machine
to control the byte alignment (IEEE ‘code-group alignment’)
of the high speed de-serializer
Enables IDLE vs. NON-IDLE detection for lane-lane
alignment. Overridden by XAUI_EN, see Table 64
Enable the elastic function of the receiver buffer
Receiver aligns data on incoming “/A/” characters (K28.3).
If disabled (default), receiver aligns data on IDLE to non-
IDLE transitions (if bit 3 set). Overridden by XAUI_EN, see
Table 64
Enable de-skew calculator of receiver Align FIFO
Enables all XAUI features per 802.3ae-2002. It is
equivalent to setting the configuration bits listed in
Table 65 (but does not change the actual value of the
corresponding MDIO registers’ bits).
Enable 3.0.14 Loopback Control
DESCRIPTION
DESCRIPTION
(2)
(3)
. Forced enabled
(4)
(3)