BBT3821-JH Intersil, BBT3821-JH Datasheet - Page 46

• Manufacturer Part Number: BBT3821-JH
• Description: IC RE-TIMER OCTAL 192-BGA
• Manufacturer: Intersil
• Type: Clock and Data Recovery (CDR)r

Specifications of BBT3821-JH

• Input: Differential
• Output: CML
• Frequency - Max: 3.1875GHz
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 192-EBGA
• Frequency-max: 3.1875GHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

IEEE PHY XS REGISTERS (4.0 TO 4.25/4.0019’H)
Note (1): This bit is latched low on a detected Fault condition. It is set high on being read.
Note (1): These bits are latched high on any Fault condition detected. They are reset low (cleared) on being read. They will also be reset low on reading the LASI
3.0.15
1.0.15
4.0.15
4.0.14
3.0.13
4.0.13
4.0.12
4.0.11
4.0.10:7
3.0.6
4.0.6
3.0.5:2
4.0.5:2
4.0.1:0
4.1.15:8
4.1.7
4.1.6:3
4.1.2
4.1.1
4.1.0
4.8.15:14
4.8.13:12
4.8.11
4.8.10
4.8.9:0
BIT(S)
BIT
BIT
registers 1.9003’h (bit 10, see Table 27) or 1.9004’h (bit 11, see Table 28)
Reset
PHY XS Loopback 1 = Enable loopback
Speed Select
Reserved
LOPOWER
Reserved
Speed Select
Speed Select
Reserved
Reserved
Local Fault
Reserved
Tx Link Up
LoPwrAble
Reserved
Device present
Reserved
TX LocalFlt
RX LocalFlt
Reserved
NAME
NAME
NAME
Table 77. IEEE PHY XS STATUS 2 DEVICE PRESENT & FAULT SUMMARY REGISTER
46
1 = PHY XS Local Fault
1 = XGXS Tx Link Up
0 = XGXS Tx Link Down
Low Power Ability
1 = reset
0 = reset done, normal
operation
0 = Normal operation
1 = 10Gbps
0 = Normal Power
1 = 10Gbps
0000 = 10Gbps
10 = Device present
1 = TX Local Fault; on Egress
channel
1 = RX Local Fault; on Ingress
channel
SETTING
SETTING
SETTING
Table 75. IEEE PHY XS CONTROL 1 REGISTER
MDIO REGISTER ADDRESSES = 4.8 (4.0008’h)
Table 76. IEEE PHY XS STATUS 1 REGISTER
MDIO REGISTER ADDRESS = 4.0 (4.0000’h)
MDIO REGISTER ADDRESS = 4.1 (4.0001’h)
BBT3821
00’h
0
0’h
1
0
0
10’b
0’b
0’b
DEFAULT
DEFAULT
0’b
0’b
1’b
00’h
0’b
1’b
0’h
0’b
(1)
DEFAULT
RO
RO/
LH
RO/
LH
RO
RO LL
RO
R/W
(1)
(1)
R/W SC Writing 1 to this bit will reset the whole chip,
R/W
RO
R/W
RO
RO
R/W
R/W
(1)
When read as “10”, it indicates that a device is present at
this device address
Lane Alignment or Byte Alignment not done, or Loss of
Signal. From Reg. 4.24
PLL lock failure (lack of RFCP/N signal)
including the MDIO registers.
Enable PHY XS loop back mode on all four lanes.
Operates at 10Gbps & above
No Low Power Mode, writes ignored
Operates at 10Gbps & above
Operates at 10Gbps
Derived from Register 4.0008’h
‘Up’ means XAUI-side signal level is OK, Byte
Synch and Lane-Lane Alignment have all
occurred
Device does not support a low power mode
DESCRIPTION
DESCRIPTION
DESCRIPTION