82P2282PF IDT, Integrated Device Technology Inc, 82P2282PF Datasheet - Page 71

• Manufacturer Part Number: 82P2282PF
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82P2282PF

• Screening Level: Industrial
• Pin Count: 100
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

IDT82P2282
on the RSIGn pin are per-timeslot aligned with the data on the RSDn
pin.
is clocked by the RSCKn. The active edge of the RSCKn used to sample
the pulse on the RSFSn is determined by the FE bit. The active edge of
the RSCKn used to update the data on the RSDn and RSIGn is deter-
mined by the DE bit. If the FE bit and the DE bit are not equal, the pulse
on the RSFSn is ahead. The speed of the RSCKn can be selected by
the CMS bit to be the same rate as the data rate on the system side
(2.048 MHz) or double the data rate (4.096 MHz). If both two links use
the RSCK[1] and RSFS[1] to output the data, the CMS bit of the two
links should be set to the same value. If the speed of the RSCKn is dou-
ble the data rate, there will be two active edges in one bit duration. In
this case, the EDGE bit determines the active edge to update the data
on the RSDn and RSIGn pins. The pulse on the RSFSn pin is always
sampled on its first active edge.
integer multiple of 125 µs to indicate the start of a frame. The active
polarity of the RSFSn is selected by the FSINV bit. If the pulse on the
RSFSn pin is not an integer multiple of 125 µs, this detection will be indi-
cated by the RCOFAI bit. If the RCOFAE bit is enabled, an interrupt will
be reported by the INT pin when the RCOFAI bit is ‘1’.
3.17.2.3
output the data from both two links. The data of Link 1 to Link 2 is byte-
interleaved output on the multiplexed bus. When the data from the two
links is output on one multiplexed bus, the sequence of the data is
arranged by setting the timeslot offset. The data from different links on
one multiplexed bus must be shifted at a different timeslot offset to avoid
data mixing.
pin and the framing pulse on the MRSFS pin are provided by the system
side and common to both two links. The signaling bits on the MRSIG pin
are per-timeslot aligned with the corresponding data on the MRSD pin.
is clocked by the MRSCK. The active edge of the MRSCK used to sam-
ple the pulse on the MRSFS is determined by the FE bit. The active
edge of the MRSCK used to update the data on the MRSD and MRSIG
is determined by the DE bit. The FE bit and the DE bit of the two links
should be set to the same value respectively. If the FE bit and the DE bit
are not equal, the pulse on the MRSFS is ahead. The MRSCK can be
selected by the CMS bit to be the same rate as the data rate on the sys-
tem side (8.192 MHz) or double the data rate (16.384 MHz). The CMS
bit of the two links should be set to the same value. If the speed of the
MRSCK is double the data rate, there will be two active edges in one bit
duration. In this case, the EDGE bit determines the active edge to
update the data on the MRSD and MRSIG pins. The pulse on the
MRSFS pin is always sampled on its first active edge.
integer multiple of 125 µs to indicate the start of a frame. The active
polarity of the MRSFS is selected by the FSINV bit. The FSINV bit of the
two links should be set to the same value. If the pulse on the MRSFS pin
is not an integer multiple of 125 µs, this detection will be indicated by the
Functional Description
In the Receive Clock Slave mode, the data on the system interface
In the Receive Clock Slave mode, the RSFSn asserts at a rate of
In the Receive Multiplexed mode, one multiplexed bus is used to
In the Receive Multiplexed mode, the timing signal on the MRSCK
In the Receive Multiplexed mode, the data on the system interface
In the Receive Multiplexed mode, the MRSFS asserts at a rate of
Receive Multiplexed Mode
71
RCOFAI bit. If the RCOFAE bit is enabled, an interrupt will be reported
by the INT pin when the RCOFAI bit is ‘1’.
3.17.2.4
SMFS bit and the CMFS bit are set to TS1 and TS16 overhead indica-
tion, the bit offset and timeslot offset are both supported in all the other
conditions. The offset is between the framing pulse on RSFSn/MRSFS
pin and the start of the corresponding frame output on the RSDn/MRSD
pin. The signaling bits on the RSIGn/MRSIG pin are always per-timeslot
aligned with the data on the RSDn/MRSD pin.
different operating modes and the configuration of the offset.
from 0 to 31 timeslots (0 & 31 are included). In Multiplexed mode, the
timeslot offset can be configured from 0 to 127 timeslots (0 & 127 are
included).
3.17.2.5
configured by the TRI bit of the corresponding link to be in high imped-
ance state or to output the processed data stream.
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Except that in the Receive Master mode, when the OHD bit, the
Refer to Chapter 3.17.1.4 Offset for the base line without offset in
In Non-multiplexed mode, the timeslot offset can be configured
The output on the RSDn/MRSD and the RSIGn/MRSIG pins can be
Offset
Output On RSDn/MRSD & RSIGn/MRSIG
August 20, 2009