82P2282PF IDT, Integrated Device Technology Inc, 82P2282PF Datasheet - Page 28

• Manufacturer Part Number: 82P2282PF
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82P2282PF

• Screening Level: Industrial
• Pin Count: 100
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

IDT82P2282
3.3
due to intersymbol interference caused by cable attenuation and distor-
tion. Usually, the Adaptive Equalizer is off in short haul applications and
is on in long haul applications, which is configured by the EQ_ON bit.
incoming signals during a selectable observation period. The observa-
tion period is selected by the UPDW[1:0] bits. A shorter observation
period allows quicker response to pulse amplitude variation, while a
longer observation period can minimize the possible overshoots.
be adjusted to achieve a normalized signal. The LATT[4:0] bits indicate
the signal attenuation introduced by the cable in approximately 2 dB per
step.
Table 5: Related Bit / Register In Chapter 3.3 & Chapter 3.4
3.5
from the received data. It is accomplished by Digital Phase Locked Loop
(DPLL). The recovered clock tracks the jitter in the data output from the
Data Slicer and keeps the phase relationship between data and clock
during the absence of the incoming pulse.
REFB_OUT. These pins output a recovered clock from the Clock and
Data Recovery function block of one of the two links. The link is selected
by the RO1[0] for REFA_OUT and with RO2[0] for REFB_OUT.
tion) on the link selected for REFA_OUT/REFB_OUT, this pin outputs
MCLK (delivered from OSCI input) or a high level signal as selected by
the REFH_LOS bit.
Functional Description
The Adaptive Equalizer can remove most of the signal distortion
The peak detector keeps on measuring the peak value of the
Based on the observed peak value for a period, the equalizer will
The Clock and Data Recovery is used to recover the clock signal
SJET provides two reference clock outputs REFA_OUT and
When Loss of Signal (LOS) is detected
ADAPTIVE EQUALIZER
CLOCK AND DATA RECOVERY
REFH_LOS
UPDW[1:0]
SLICE[1:0]
LATT[4:0]
EQ_ON
Bit
(Chapter 3.7.3 LOS Detec-
Reference Clock Output Control
Receive Configuration 1
Receive Configuration 2
Line Status Register 1
Register
28
J1 and E1 modes. In long haul application, the receive sensitivity is -36
dB in T1/J1 mode or -43 dB in E1 mode.
3.4
space according to the amplitude of the input signals. The criteria of
mark or space generation are based on a selected ratio of the incoming
signal amplitude against the peak value detected during the observation
period. This ratio is selected by the SLICE[1:0] bits. The output of the
Data Slicer is forwarded to the Clock and Data Recovery unit.
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
In short haul application, the receive sensitivity is -10 dB in both T1/
The Data Slicer is used to generate a standard amplitude mark or a
DATA SLICER
Address (Hex)
02A, 12A
029, 129
037, 137
03E,13E
August 20, 2009