82P2282PF IDT, Integrated Device Technology Inc, 82P2282PF Datasheet - Page 275
82P2282PF
Manufacturer Part Number
82P2282PF
Description
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet
1.82P2282PF.pdf
(381 pages)
Specifications of 82P2282PF
Screening Level
Industrial
Pin Count
100
Mounting
Surface Mount
Package Type
TQFP
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Lead Free Status / RoHS Status
Not Compliant
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E1 RBIF TS Offset (049H, 149H)
TSOFF[6:0]:
are set to TS1 and TS16 overhead indication, the timeslot offset is supported in all the other conditions.
start of the corresponding frame output on the RSDn/MRSD pin. The signaling bits on the RSIGn/MRSIG pin are always per-timeslot aligned with the
data on the RSDn/MRSD pin.
set can be configured from 0 to 127 timeslots (0 & 127 are included).
E1 RBIF Bit Offset (04AH, 14AH)
EDGE:
BOFF[2:0]:
are set to TS1 and TS16 overhead indication, the bit offset is supported in all the other conditions.
corresponding frame output on the RSDn/MRSD pin. The signaling bits on the RSIGn/MRSIG pin are always per-channel aligned with the data on the
RSDn/MRSD pin.
Programming Information
IDT82P2282
Bit Name
Bit Name
Default
Default
Bit No.
Bit No.
Type
Type
Except that in the Receive Master mode, when the OHD bit (b3, E1-048H,...), the SMFS bit (b2, E1-048H,...) and the CMFS bit (b1, E1-048H,...)
These bits give a binary number to define the timeslot offset. The timeslot offset is between the framing pulse on the RSFSn/MRSFS pin and the
In Non-multiplexed mode, the timeslot offset can be configured from 0 to 31 timeslots (0 & 31 are included). In Multiplexed mode, the timeslot off-
This bit is valid when the CMS bit (b1, E1-046H,...) is ‘1’.
= 0: The first active edge of RSCKn/MRSCK is selected to update the data on the RSDn/MRSD and RSIGn/MRSIG pins.
= 1: The second active edge of RSCKn/MRSCK is selected to update the data on the RSDn/MRSD and RSIGn/MRSIG pins.
Except that in the Receive Master mode, when the OHD bit (b3, E1-048H,...), the SMFS bit (b2, E1-048H,...) and the CMFS bit (b1, E1-048H,...)
These bits give a binary number to define the bit offset. The bit offset is between the framing pulse on the RSFSn/MRSFS pin and the start of the
Reserved
7
7
TSOFF6
R/W
6
0
6
Reserved
TSOFF5
R/W
5
0
5
TSOFF4
R/W
4
0
4
275
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
TSOFF3
EDGE
R/W
R/W
3
0
3
0
TSOFF2
BOFF2
R/W
R/W
2
0
2
0
TSOFF1
BOFF1
R/W
R/W
1
0
1
0
August 20, 2009
TSOFF0
BOFF0
R/W
R/W
0
0
0
0
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