82P2282PF IDT, Integrated Device Technology Inc, 82P2282PF Datasheet - Page 18

• Manufacturer Part Number: 82P2282PF
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82P2282PF

• Screening Level: Industrial
• Pin Count: 100
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

IDT82P2282
Pin Description
CLK_SEL[0]
CLK_SEL[1]
CLK_SEL[2]
REFA_OUT
REFB_OUT
CLK_GEN
RESET
OSCO
Name
REFR
GPIO
THZ
INT
CS
Output / Input
Output
Output
Output
Output
Output
Output
Type
Input
Input
Input
Input
Pin No.
94
85
86
87
81
90
92
84
49
48
1
2
9
OSCO: Crystal Oscillator Output
This pin outputs the inverted, buffered clock input from OSCI.
CLK_SEL[2:0]: Clock Selection
These three pins select the input clock signal:
When the CLK_SEL[2] pin is low, the input clock signal is N X 1.544 MHz;
when the CLK_SEL[2] pin is high, the input clock signal is N X 2.048 MHz.
When the CLK_SEL[1:0] pins are ‘00’, the N is 1;
When the CLK_SEL[1:0] pins are ‘01’, the N is 2;
When the CLK_SEL[1:0] pins are ‘10’, the N is 3;
When the CLK_SEL[1:0] pins are ‘11’, the N is 4.
CLK_SEL[2:0] are Schmitt-trigger inputs.
CLK_GEN: Clock Generator
This pin outputs the 1.544/2.048 MHz clock signal generated by the Clock Generator.
REFA_OUT: Reference Clock Output A
The frequecy is 2.048 MHz (E1) or 1.544 MHz (T1/J1).
When no LOS is detected, this pin outputs a recovered clock from the Clock and Data Recovery function block of one
of the two links. The link is selected by the RO10 bit (b0, T1/J1-007H / b0, E1-007H).
When LOS is detected, this pin outputs MCLK or high level, as selected by the REFH_LOS bit (b0, T1/J1-03EH, b0,
E1-03EH).
Note: MCLK is a clock derived from OSCI using an internal PLL, and the frequency is 2.048 MHz (E1) or 1.544 MHz
(T1/J1).
REFB_OUT: Reference Clock Output B
The frequecy is 2.048 MHz(E1) or 1.544 MHz(T1/J1).
When no LOS is detected, this pin outputs a recovered clock from the Clock and Data Recovery function block of one
of the two links. The link is selected by the RO20 bit (b3, T1/J1-007H / b3, E1-007H).
When LOS is detected, this pin outputs MCLK or high level, as selected by the REFH_LOS bit (b0, T1/J1-03EH/ b0,
E1-03EH).
RESET: Reset (Active Low)
A low pulse for more than 100 ns on this pin resets the device. All the registers are accessible 2 ms after the reset.
Reset can only be applied when the clock on the OSCI pin is available.
The RESET pin is a Schmitt-trigger input with a weak pull-up resistor. The OSCI clock must exist when the device is
reset.
General Purpose I/O
This pin can be defined as input pin or output pin by the DIR0 bit (b0, T1/J1-006H / b0, E1-006H). When the pin is
input, its polarity is indicated by the LEVEL0 bit (b2, T1/J1-006H / b2, E1-006H). When the pin is output, its polarity is
controlled by the LEVEL0 bit (b2, T1/J1-006H / b2, E1-006H).
GPIO is a Schmitt-trigger input/output with a pull-up resistor.
THZ: Transmit High-Z
A high level on this pin puts all the TTIPn/TRINGn pins into high impedance state.
THZ is a Schmitt-trigger input.
INT: Interrupt (Active Low)
This is the open drain, active low interrupt output. This pin will stay low until all the active unmasked interrupt indication
bits are cleared.
REFR:
This pin should be connected to ground via an external 10K resistor.
CS: Chip Select (Active Low)
This pin must be asserted low to enable the microprocessor interface. The signal must be asserted high at least once
after power up to clear the internal test modes. A transition from high to low must occur on this pin for each Read/Write
operation and can not return to high until the operation is completed.
CS is a Schmitt-trigger input.
Control Interface
18
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Description
August 20, 2009