82P2282PF IDT, Integrated Device Technology Inc, 82P2282PF Datasheet - Page 65

• Manufacturer Part Number: 82P2282PF
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82P2282PF

• Screening Level: Industrial
• Pin Count: 100
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

IDT82P2282
3.17
received data stream to the system backplane. The data from the two
links can be aligned with each other or be output independently. The tim-
ing clocks and framing pulses can be provided by the system backplane
or obtained from the far end. The Receive System Interface supports
various configurations to meet various requirements in different applica-
tions.
3.17.1
multiplexed Mode or Multiplexed Mode. In the Non-multiplexed Mode,
the RSDn pin is used to output the received data from each link at the bit
rate of 1.544 Mb/s or 2.048 Mb/s (T1/J1 mode E1 rate). While in the Mul-
tiplexed Mode, the received data from the two links is converted to 2.048
Mb/s format and byte interleaved to form one high speed data stream
and output on the MRSD pin at the bit rate of 8.192 Mb/s.
Table 39: Operating Modes Selection In T1/J1 Receive Path
3.17.1.1
signal on the RSCKn pin and framing pulse on the RSFSn pin to output
the data on each RSDn pin. The signaling bits on the RSIGn pin are per-
channel aligned with the data on the RSDn pin.
face is clocked by the RSCKn. The active edge of the RSCKn used to
update the pulse on the RSFSn is determined by the FE bit. The active
edge of the RSCKn used to update the data on the RSDn and RSIGn is
determined by the DE bit. If the FE bit and the DE bit are not equal, the
pulse on the RSFSn is ahead.
F-bit or the first F-bit of every SF/ESF/T1 DM/SLC-96 multi-frame. In SF
format, the RSFSn can also indicate every second F-bit or the first F-bit
of every second SF multi-frame. All the indications are selected by the
Functional Description
NOTE:
1. When the G56K, GAP bits in RPLC indirect registers are set, the PCCE bit must be set to ‘1’.
2. The MAP[1:0] bits can not be set to ‘00’ in the Receive Multiplexed mode.
RMUX RMODE
0
1
The Receive System Interface determines how to output the
In T1/J1 mode, the Receive System Interface can be set in Non-
In the Receive Clock Master mode, each link uses its own timing
In the Receive Clock Master mode, the data on the system inter-
In the Receive Clock Master mode, the RSFSn can indicate each
RECEIVE SYSTEM INTERFACE
T1/J1 MODE
X
0
1
Receive Clock Master Mode
G56K, GAP /
not all 0s
FBITGAP
00 / 0
X
X
1
MAP[1:0]
00
01
10
01
10
11
11
X
2
Receive Clock Master Full T1/J1
Receive Clock Master Fractional T1/J1
Receive Clock Slave - T1/J1 Rate
Receive Clock Slave - T1/J1 Mode E1 Rate per G.802
Receive Clock Slave - T1/J1 Mode E1 Rate per One Filler Every Four CHs
Receive Clock Slave - T1/J1 Mode E1 Rate per Continuous CHs
Receive Multiplexed - T1/J1 Mode E1 Rate per G.802
Receive Multiplexed - T1/J1 Mode E1 Rate per One Filler Every Four CHs
Receive Multiplexed - T1/J1 Mode E1 Rate per Continuous CHs
Operating Mode
65
(M)RSCKn/(M)RSFSn. This clock is derived from line side signal or
MCLK (When LOSS).
the entire T1/J1 frame, the Receive System Interface is in Receive Clock
Master Full T1/J1 mode. If only the clocks aligned to the selected chan-
nels are output on RSCKn, the Receive System Interface is in Receive
Clock Master Fractional T1/J1 mode.
(M)RSFSn to the device. To avoid shatter data, this clock should keep
the same source with line side. If the backplane data rate is 2.048 Mb/s,
means T1 mode E1 rate, the receive data(1.544 Mb/s) should be
mapped to 2.048 Mb/s,there are 3 kinds of mapping schemes.
two links should be converted to 2.048 Mb/s format first and then multi-
plexed to 8.192 Mb/s, there are still 3 kinds of schemes to be selected.
each link into various operating modes and the pins’ direction of the
Receive System Interface in different operating modes.
CMFS bit and the ALTIFS bit. The active polarity of the RSFSn is
selected by the FSINV bit.
Clock Master Full T1/J1 mode and Receive Clock Master Fractional T1/
J1 mode.
3.17.1.1.1
Master mode, the special feature in this mode is that the RSCKn is a
standard 1.544 MHz clock, and the data in the F-bit and all 24 channels
in a standard T1/J1 frame are clocked out by the RSCKn.
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
In the Receive Clock Master mode, the device outputs clock
In the Receive Clock Master mode, if RSCKn outputs pulses during
In the Receive Clock Slave mode, outside inputs clock (M)RSCKn/
In the Receive Multiplexed mode, since the received data from the
Table 39 summarizes how to set the Receive System Interface of
The Receive Clock Master mode includes two sub-modes: Receive
Besides all the common functions described in the Receive Clock
Receive Clock Master Full T1/J1 Mode
MRSCK, MRSFS
RSCKn, RSFSn
Receive System Interface Pin
Input
X
August 20, 2009
RSCKn, RSFSn,
MRSD, MRSIG
RSDn, RSIGn
RSDn, RSIGn
Output