82P2282PF IDT, Integrated Device Technology Inc, 82P2282PF Datasheet
82P2282PF
Specifications of 82P2282PF
Related parts for 82P2282PF
82P2282PF Summary of contents
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Dual T1/E1/J1 Long Haul / Short Haul Transceiver IDT82P2282 6024 Silver Creek Valley Road, San Jose, CA 95138 Telephone: (800) 345-7015 • TWX: 910-338-2070 • FAX: (408) 284-2775 © 2008 Integrated Device Technology, Inc. Version 10 August 20, 2009 Printed ...
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Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best pos- sible product. IDT does not assume any ...
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FEATURES ............................................................................................................................................................................ 12 APPLICATIONS..................................................................................................................................................................... 12 BLOCK DIAGRAM ................................................................................................................................................................ 13 1 PIN ASSIGNMENT ........................................................................................................................................................... 14 2 PIN DESCRIPTION .......................................................................................................................................................... 15 3 FUNCTIONAL DESCRIPTION ......................................................................................................................................... 22 3 MODE SELECTION ................................................................................................................................................................... 24 3.2 RECEIVER IMPEDANCE MATCHING .......................................................................................................................................................... 25 ...
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IDT82P2282 3.8.2.3.3 National Bit Extraction ................................................................................................................................... 46 3.8.2.3.4 National Bit Codeword Extraction .................................................................................................................. 46 3.8.2.3.5 Extra Bit Extraction ........................................................................................................................................ 46 3.8.2.3.6 Remote Signaling Multi-Frame Alarm Indication Bit Extraction ..................................................................... 46 3.8.2.3.7 Sa6 Code Detection Per ETS 300 233 .......................................................................................................... 46 ...
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IDT82P2282 3.18.2.4 Offset ................................................................................................................................................................................ 80 3.19 TRANSMIT PAYLOAD CONTROL ............................................................................................................................................................... 81 3.20 FRAME GENERATOR .................................................................................................................................................................................. 82 3.20.1 Generation ...................................................................................................................................................................................... 82 3.20.1 Mode .................................................................................................................................................................... 82 3.20.1.1.1 Super Frame (SF) Format ............................................................................................................................. 82 3.20.1.1.2 Extended Super Frame (ESF) Format ...
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IDT82P2282 4 OPERATION ................................................................................................................................................................... 108 4.1 POWER-ON SEQUENCE ............................................................................................................................................................................ 108 4.2 RESET ......................................................................................................................................................................................................... 108 4.3 RECEIVE / TRANSMIT PATH POWER DOWN .......................................................................................................................................... 108 4.4 MICROPROCESSOR INTERFACE ............................................................................................................................................................ 109 4.4.1 SPI Mode ....................................................................................................................................................................................... 109 4.4.2 Parallel Microprocessor Interface .............................................................................................................................................. 110 4.5 ...
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IDT82P2282 7.12.1.2 Write Cycle Specification ................................................................................................................................................ 377 7.12.2 Intel Non-Multiplexed Mode ......................................................................................................................................................... 378 7.12.2.1 Read Cycle Specification ............................................................................................................................................... 378 7.12.2.2 Write Cycle Specification ................................................................................................................................................ 379 7.12.3 SPI Mode ....................................................................................................................................................................................... 380 ORDERING INFORMATION .......................................................................................................................................... 381 DOCUMENT HISTORY .................................................................................................................................................. 381 Table of ...
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Table 1: Operating Mode Selection ........................................................................................................................................................................... 24 Table 2: Related Bit / Register In Chapter 3.1 ........................................................................................................................................................... 24 Table 3: Impedance Matching Value For The Receiver ............................................................................................................................................. 25 Table 4: Related Bit / Register In Chapter 3.2 ........................................................................................................................................................... 27 Table ...
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IDT82P2282 Table 49: Interrupt Summary In E1 Mode .................................................................................................................................................................... 85 Table 50: Related Bit / Register In Chapter 3.20.1.2 ................................................................................................................................................... 86 Table 51: Related Bit / Register In Chapter 3.20.2.1 ................................................................................................................................................... 87 Table 52: Related Bit / Register In Chapter ...
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Figure 1. 100-Pin TQFP (Top View) ............................................................................................................................................................................ 14 Figure 2. Receive / Transmit Line Circuit .................................................................................................................................................................... 25 Figure 3. Receive Path Monitoring (Twisted Pair) ....................................................................................................................................................... 26 Figure 4. Transmit Path Monitoring (Twisted Pair) ...................................................................................................................................................... 26 Figure 5. Receive Path Monitoring ...
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IDT82P2282 Figure 49. Motorola Non-Multiplexed Mode Read Cycle ........................................................................................................................................... 376 Figure 50. Motorola Non-Multiplexed Mode Write Cycle ........................................................................................................................................... 377 Figure 51. Intel Non-Multiplexed Mode Read Cycle .................................................................................................................................................. 378 Figure 52. Intel Non-Multiplexed Mode Write Cycle .................................................................................................................................................. 379 Figure 53. SPI ...
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... Supports Analog Loopback, Digital Loopback and Remote Loop- back • Each receiver and transmitter can be individually powered down FRAMER • Each link can be configured as T1 • Frame alignment/generation for T1 (per ITU-T G.704, TA-TSY- 000278, TR-TSY-000008), E1 (per ITU-T G.704), J1 (per JT G.704) and un-framed mode • ...
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IDT82P2282 BLOCK DIAGRAM DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER 13 REFB_OUT REFA_OUT CLK_SEL[2:0] OSCO OSCI CLK_GEN GPIO RESET THZ A[8:0] D[7:1] D[0]/SDO CS REFR RW/WR/SDI DS/RD/SCLK MPM SPIEN INT TDO TDI TMS TCK TRST August 20, 2009 ...
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IDT82P2282 1 PIN ASSIGNMENT GPIO 1 THZ 2 VDDDC[3] 3 GNDDC[3] 4 GNDAP 5 VDDAP 6 GNDAB 7 VDDAB 8 REFR 9 GNDAR[2] 10 RRING[2] 11 RTIP[2] 12 VDDAR[2] 13 VDDAT[2] 14 GNDAT[2] 15 GNDAX[2] 16 TRING[2] 17 TTIP[2] 18 ...
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IDT82P2282 2 PIN DESCRIPTION Name Type Pin No. RTIP[1] Input 27 RTIP[2] 12 RRING[1] 28 RRING[2] 11 TTIP[1] Output 21 TTIP[2] 18 TRING[1] 22 TRING[2] 17 RSD[1] / MRSD Output 79 RSD[2] 71 RSIG[1] / MRSIG Output 78 RSIG[2] 70 ...
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IDT82P2282 Name Type Pin No. RSFS[1] / MRSFS Output / Input 77 RSFS[2] 69 RSCK[1] / MRSCK Output / Input 80 RSCK[2] 72 TSD[1] / MTSD Input 75 TSD[2] 67 Pin Description DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER ...
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IDT82P2282 Name Type Pin No. TSIG[1] / MTSIG Input 74 TSIG[2] 66 TSFS[1] / MTSFS Output / Input 73 TSFS[2] 65 TSCK[1] / MTSCK Output / Input 76 TSCK[2] 68 OSCI Input 95 Pin Description DUAL T1/E1/J1 LONG HAUL / ...
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IDT82P2282 Name Type Pin No. OSCO Output 94 CLK_SEL[0] Input 85 CLK_SEL[1] 86 CLK_SEL[2] 87 CLK_GEN Output 81 REFA_OUT Output 90 REFB_OUT Output 92 Input 84 RESET GPIO Output / Input 1 THZ Input 2 INT Output 49 REFR Output ...
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IDT82P2282 Name Type Pin No. A[0] Input 52 A[1] 53 A[2] 54 A[3] 55 A[4] 56 A[5] 57 A[6] 60 A[7] 62 A[8] 63 D[0] / SDO Output / Input 34 D[1] 35 D[2] 36 D[3] 37 D[4] 38 D[5] ...
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IDT82P2282 Name Type Pin No. TMS Input 100 TCK Input 98 TDI Input 99 TDO High-Z 96 VDDDIO[0] Power 93 VDDDIO[1] 40 VDDDIO[2] 64 GNDDIO[0] Ground 89 GNDDIO[1] 44 GNDDIO[2] 59 VDDDC[0] Power 91 VDDDC[1] 42 VDDDC[2] 61 VDDDC[3] 3 ...
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IDT82P2282 Name Type Pin No Pin Description DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER IC: Internal Connected These pins are for IDT use only and should be connected to ...
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... The transmit path of each transceiver can be configured to generate SF, ESF SLC- 96. The framer can also be disabled (unframed mode). The Framer can transmit Yellow alarm and AIS alarm. Inband loopback codes and bit ori- ented message can be transmitted three HDLC links (in ESF and ...
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IDT82P2282 TEST AND DIAGNOSES To facilitate the testing and diagnostic functions, Analog Loopback, Remote Digital Loopback, Remote Loopback, Local Digital Loopback, Payload Loopback and System Loopback are also integrated in the IDT82P2282. A programmable pseudo random bit sequence can be ...
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IDT82P2282 3 MODE SELECTION Each link in the IDT82P2282 can be configured as a duplex T1 transceiver duplex E1 transceiver duplex J1 transceiver. When mode, Super Frame ...
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IDT82P2282 3.2 RECEIVER IMPEDANCE MATCHING The receiver impedance matching can be realized by using internal impedance matching circuit or external impedance matching circuit. When the R_TERM[2] bit is ‘0’, the internal impedance matching circuit is enabled. 100 Ω, 110 Ω, ...
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IDT82P2282 DSX cross connect point R DSX cross connect point Functional Description DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER RTIPn R RRINGn R RTIPn r RRINGn Figure 3. Receive Path Monitoring (Twisted Pair RTIPn r RRINGn Figure ...
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IDT82P2282 DSX cross connect point DSX cross connect point Table 4: Related Bit / Register In Chapter 3.2 Bit R_TERM[2:0] Transmit And Receive Termination Configuration MG[1:0] Functional Description DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER RRINGn R RRINGn Figure ...
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IDT82P2282 3.3 ADAPTIVE EQUALIZER The Adaptive Equalizer can remove most of the signal distortion due to intersymbol interference caused by cable attenuation and distor- tion. Usually, the Adaptive Equalizer is off in short haul applications and long ...
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IDT82P2282 3.6 RECEIVE JITTER ATTENUATOR The Receive Jitter Attenuator of each link can be chosen to be used or not. This selection is made by the RJA_E bit. The Jitter Attenuator consists of a FIFO and a DPLL, as shown ...
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IDT82P2282 3.7 DECODER 3.7.1 LINE CODE RULE 3.7.1 Mode In T1/J1 mode, the AMI and B8ZS line code rules are provided. The selection is made by the R_MD bit. 3.7.1.2 E1 Mode In E1 mode, the AMI ...
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IDT82P2282 clock RTIPn RRINGn clock RTIPn 2 RRINGn 1 clock RTIPn 1 RRINGn 2 Figure 10. HDB3 Code Violation & Excessive Zero Error 3.7.3 LOS DETECTION The Loss of Signal (LOS) Detector monitors the amplitude and den- sity of the ...
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IDT82P2282 Table 9: LOS Condition In T1/J1 Mode Loss of Signal in T1/J1 Mode ANSI T1.231 Amplitude below 800 mVpp LOS Detected Continuous Intervals 175 bits Amplitude above 1 Vpp LOS 12.5% (16 marks in a hopping Cleared Mark Density ...
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IDT82P2282 Table 11: Related Bit / Register In Chapter 3.7 Bit R_MD EXZ_ERR EXZ_DEF CNT_MD CNT_TRF CNTL[7:0] CNTH[7:0] CV_IS EXZ_IS CNTOV_IS CV_IE EXZ_IE CNT_IE LAC RAISE LOS_S LOS_IES LOS_IS LOS_IE LOS[4:0] Functional Description DUAL T1/E1/J1 LONG HAUL / SHORT HAUL ...
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... T1 mode. The Frame Processor acquires frame alignment per ITU-T requirement. When frame alignment is achieved, the Framer Processor contin- ues to monitor the received data stream. The Frame Processor will declare framing bit errors or bit error events if any. The Frame Processor can also detect out-of-frame events based on selected criteria ...
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IDT82P2282 3.8.1.1.2 Extended Super Frame (ESF) Format The structure of T1/J1 ESF is illustrated in Table 13. The ESF is made frames. Each frame consists of one overhead bit (F-bit) and 24 8-bit channels. The F-bit in ...
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IDT82P2282 3.8.1.1.3 T1 Digital Multiplexer (DM) Format (T1 only) The structure illustrated in Table 14. The made frames. Each frame consists of one overhead bit (F-bit) and 24 8-bit channels. ...
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IDT82P2282 3.8.1.1.4 Switch Line Carrier - 96 (SLC-96) Format (T1 only) The structure of SLC-96 is illustrated in Table 15. The SLC-96 is made SFs, but some F-bit are used as Concentrator Bits, Spoiler Bits, Maintenance Bits, ...
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IDT82P2282 3.8.1.2 Error Event And Out Of Synchronization Detection After the frame is in synchronization, the Frame Processor contin- ues to monitor the received data stream to detect errors and judge out of synchronization. 3.8.1.2.1 Super Frame ...
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IDT82P2282 Once resynchronized, if the new-found F bit position differs from the previous one, the change of frame alignment event is generated. This event is captured by the COFAI bit and is forwarded to the Perfor- mance Monitor. 3.8.1.3 Overhead ...
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IDT82P2282 Table 17: Related Bit / Register In Chapter 3.8.1 Bit UNFM REFEN REFR REFCRCE MIMICC M2O[1:0] DDSC OOFV MIMICI EXCRCERI OOFI RMFBI SFEI BEEI FERI COFAI OOFE RMFBE SFEE BEEE FERE COFAE C[11:1] M[3:1] A[2:1] S[4:1] SCAI SCSI SCMI ...
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... Sa4 to Sa8 can also be extracted and stored in registers, and updated every CRC Sub Multi-Frame. The Framer Processor identifies the Remote Alarm bit (bit 3 of TS0 of NFAS frames) and Remote Signaling Multi-Frame Alarm (bit 6 of TS16 of the frame 0 of the Signaling Multi-Frame). The ‘de-bounced’ ...
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IDT82P2282 search for Basic Fframe alignment pattern > 914 CRC search for CRC Multi-Frame errors in alignment pattern if CRCEN = one 1 (refer to CRC Multi-Frame) second Start 8ms and 400ms timer find 2 CRC Multi-Frame alignment patterns within ...
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IDT82P2282 3.8.2.1 Synchronization Searching 3.8.2.1.1 Basic Frame The algorithm used to search for the E1 Basic Frame alignment pattern (as shown in Figure 12) meets the ITU-T Recommendation G.706 4.1.2 and 4.2. Generally performed by detecting a successive ...
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IDT82P2282 3.8.2.1.2 CRC Multi-Frame The CRC Multi-Frame is provided to enhance the ability of verifying the data stream. The structure of TS0 of the CRC Multi-Frame is illus- trated in Table 18. A CRC Multi-Frame consists of 16 continuous Basic ...
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IDT82P2282 3.8.2.1.3 CAS Signaling Multi-Frame After the Basic Frame has been synchronized, the Frame Proces- sor starts to search for CAS Signaling Multi-Frame alignment signal if the CASEN bit is ‘1’. The Signaling Multi-Frame alignment pattern is located in the ...
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IDT82P2282 10. NT CRC Error (per ETS 300 233): If the 4-bit Sa6 codeword of a CRC Sub Multi-Frame is matched with ‘0010’ or ‘0011’, the Network Terminal CRC Error event is generated. This error event is captured by the ...
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IDT82P2282 pared if the Sa6SYN bit is ‘1’ matched code is detected, the corresponding indication bit in the Sa6 Code Indication register will be set. 3.8.2.4 V5.2 Link The V5.2 link ID signal, i.e., 2 out of 3 ...
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IDT82P2282 Table 21: Related Bit / Register In Chapter 3.8.2 Bit Register UNFM REFEN FRMR Mode 0 REFCRCE REFR CRCEN C2NCIWCK CASEN WORDERR FRMR Mode 1 CNTNFAS BIT2C SMFASC TS16C OOFV OOCMFV OOOFV FRMR Status C2NCIWV OOSMFV EXCRCERI C2NCIWI OOFI ...
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IDT82P2282 3.9 PERFORMANCE MONITOR 3.9.1 T1/J1 MODE Several internal counters are used to count different events for per- formance monitoring. For different framing format, the counters are used differently. The overflow of each counter is reflected by an Overflow Indi- ...
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IDT82P2282 Table 23: Related Bit / Register In Chapter 3.9.1 Bit LCV[15:0] FER[11:0] COFA[2:0] OOF[4:0] PRGD[15:0] CRCE[9:0] DDSE[9:0] LCVOVI FEROVI COFAOVI OOFOVI PRGDOVI CRCOVI DDSOVI LCVOVE FEROVE COFAOVE OOFOVE PRGDOVE CRCOVE DDSOVE LINKSEL ADDR[3:0] DATA[7:0] UPDAT AUTOUPD Note ...
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IDT82P2282 3.9.2 E1 MODE Several internal counters are used to count different events for per- formance monitoring. For different framing format, the counters are used differently. The overflow of each counter is reflected by an Overflow Indi- cation Bit, and ...
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IDT82P2282 Table 25: Related Bit / Register In Chapter 3.9.2 Bit LCV[15:0] FER[11:0] CRCE[9:0] FEBE[9:0] COFA[2:0] OOF[4:0] PRGD[15:0] TFEBE[9:0] TCRCE[9:0] LCVOVI FEROVI CRCOVI FEBEOVI COFAOVI OOFOVI PRGDOVI TFEBEOVI TCRCOVI LCVOVE FEROVE CRCOVE FEBEOVE COFAOVE OOFOVE PRGDOVE TFEBEOVE TCRCOVE LINKSEL ADDR[3:0] ...
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IDT82P2282 3.10 ALARM DETECTOR 3.10.1 T1/J1 MODE The RED alarm, Yellow alarm and Blue alarm are detected in this block (refer to Table 26). Table 26: RED Alarm, Yellow Alarm & Blue Alarm Criteria Declare Condition The out of SF/ESF/T1 ...
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IDT82P2282 Table 27: Related Bit / Register In Chapter 3.10.1 Bit REDDTH[7:0] REDCTH[7:0] YELDTH[7:0] YELCTH[7:0] AISDTH[7:0] AISCTH[7:0] RED YEL AIS REDI YELI AISI REDE YELE AISE Functional Description DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER Register RED Declare Threshold ...
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IDT82P2282 3.10.2 E1 MODE The Remote alarm, Remote Signaling Multi-Frame alarm, RED alarm, AIS alarm, AIS in TS16 and LOS in TS16 are detected in this block. The Remote Alarm Indication bit is the A bit (refer to Table 18). ...
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IDT82P2282 3.11 HDLC RECEIVER The HDLC Receiver extracts the HDLC data stream from the selected position and processes the data according to the selected mode. 3.11.1 HDLC CHANNEL CONFIGURATION In T1/J1 mode ESF & formats, three HDLC Receivers ...
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IDT82P2282 - The extracted HDLC packet does not consist of an integral num- ber of octets (Hex) abort sequence is received; - Address is not matched if the address comparison is enabled. (The address comparison mode is ...
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IDT82P2282 Table 31: Related Bit / Register In Chapter 3.11.2 Bit RHDLCM RHDLC1 Control Register / RHDLC2 Control Register / RHDLC3 Control ADRM[1:0] RRST HA[7:0] RHDLC1 High Address / RHDLC2 High Address / RHDLC3 High Address LA[7:0] RHDLC1 Low Address ...
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IDT82P2282 3.12 BIT-ORIENTED MESSAGE RECEIVER The Bit-Oriented Message (BOM) can only be received in the ESF format in T1/J1 mode. The BOM pattern is ‘111111110XXXXXX0’ which occupies the DL of the F-bit in the ESF format (refer to Table 13). ...
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... Framer 6 & signaling multi-frame are recognized as ‘A’ and the signaling bits on Framer 12 & 24 are recognized as ‘B’. Only the sig- naling bits A & B will be saved in the Extracted Signaling Data/Extract Enable register, and the C & ...
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IDT82P2282 Channel RSDn/MRSD RSIGn/MRSIG 3.15.2 E1 MODE In Signaling Multi-Frame, the signaling bits are located in TS16 (refer to Figure 13), which are Channel Associated Signalings (CAS). ...
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IDT82P2282 Table 35: Related Bit / Register In Chapter 3.15 Bit EXTRACT A,B,C,D DEB FREEZE SIGF (T1/J1 only) SIGE COSI[X] (1 ≤ X ≤ T1/J1) (1 ≤ X ≤ E1) ADDRESS[6:0] RWN D[7:0] BUSY Note: * ...
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IDT82P2282 3.16 RECEIVE PAYLOAD CONTROL Different test patterns can be inserted in the received data stream or the received data stream can be extracted to the PRBS Generator/ Detector for test in this block. To enable all the functions in ...
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IDT82P2282 read from or written into the specified indirect register is determined by the RWN bit and the data is in the D[7:0] bits. The access status is indi- Table 38: Related Bit / Register In Chapter 3.16 Bit PCCE ...
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IDT82P2282 3.17 RECEIVE SYSTEM INTERFACE The Receive System Interface determines how to output the received data stream to the system backplane. The data from the two links can be aligned with each other or be output independently. The tim- ing ...
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IDT82P2282 3.17.1.1.2 Receive Clock Master Fractional T1/J1 Mode Besides all the common functions described in the Receive Clock Master mode, the special feature in this mode is that the RSCKn is a gapped 1.544 MHz clock (no clock signal during ...
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IDT82P2282 1.544 CH1 CH2 F Mb/s 2.048 TS0 TS1 TS2 Mb/s filler the 8th bit Figure 20. T1/ Format Mapping - Continuous Channels Mode In the Receive Clock Slave mode, the timing signal on the RSCKn pin and ...
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IDT82P2282 Receive Clock Slave mode / Receive Multiplexed mode: RSFSn / MRSFS RSCKn / MRSCK RSDn / MRSD Receive Clock Master mode: RSFSn / MRSFS RSCKn / MRSCK RSDn / MRSD Figure 21. No Offset When & ...
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IDT82P2282 Receive Clock Slave mode / Receive Multiplexed mode: RSFSn / MRSFS RSCKn / MRSCK RSDn / MRSD Receive Clock Master mode: RSFSn / MRSFS RSCKn / MRSCK RSDn / MRSD Figure 23. No Offset When & ...
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IDT82P2282 In Non-multiplexed mode, the channel offset can be configured from channels (0 & 23 are included). In Multiplexed mode, the channel offset can be configured from 0 to 127 channels (0 & 127 are included). 3.17.1.5 ...
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IDT82P2282 on the RSIGn pin are per-timeslot aligned with the data on the RSDn pin. In the Receive Clock Slave mode, the data on the system interface is clocked by the RSCKn. The active edge of the RSCKn used to ...
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IDT82P2282 Table 41: Related Bit / Register In Chapter 3.17 Bit Register RMUX Backplane Global Configuration RSLVCK RMODE RBIF Mode MAP[1:0] (T1/J1 only) G56K Channel Control (for T1/ J1) / Timeslot Control (for E1) GAP FBITGAP (T1/J1 ...
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IDT82P2282 3.18 TRANSMIT SYSTEM INTERFACE The Transmit System Interface determines how to input the data to the device. The data input to the two links can be aligned with each other or input independently. The timing clocks and framing pulses ...
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IDT82P2282 by selecting the G56K & GAP bits in the Transmit Payload Control. The data in the corresponding gapped duration is a Don't Care condition. 3.18.1.2 Transmit Clock Slave Mode In the Transmit Clock Slave mode, the system data rate ...
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IDT82P2282 the 8th bit discarded 2.048 TS0 TS1 TS2 Mb/s 1.544 CH1 CH2 F Mb/s Figure 27 T1/J1 Format Mapping - Continuous Channels Mode In the Transmit Clock Slave mode, the timing signal on the TSCKn pin and ...
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IDT82P2282 3.18.1.4 Offset Bit offset and channel offset are both supported in all the operating modes. The offset is between the framing pulse on the TSFSn/MTSFS pin and the start of the corresponding frame input on the TSDn/MTSD Transmit Clock ...
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IDT82P2282 Transmit Clock Slave mode / Transmit Multiplexed mode: TSFSn / MTSFS TSCKn / MTSCK TSDn / MTSD Transmit Clock Master mode: TSFSn / MTSFS TSCKn / MTSCK TSDn / MTSD Figure 30. No Offset When & ...
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IDT82P2282 In Non-multiplexed mode, the channel offset can be configured from channels (0 & 23 are included). In Multiplexed mode, the channel offset can be configured from 0 to 127 channels (0 & 127 are included). DUAL ...
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IDT82P2282 3.18.2 E1 MODE In E1 mode, the Transmit System Interface can be set in Non-multi- plexed Mode or Multiplexed Mode. In the Non-multiplexed Mode, the TSDn pin is used to input the data to each link at the bit ...
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IDT82P2282 selected by the FSINV bit. If the pulse on the TSFSn pin is not an integer multiple of 125 µs, this detection will be indicated by the TCOFAI bit. If the TCOFAE bit is enabled, an interrupt will be ...
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IDT82P2282 3.19 TRANSMIT PAYLOAD CONTROL Different test patterns can be inserted in the data stream to be transmitted or the data stream to be transmitted can be extracted to the PRBS Generator/Detector for test in this block. To enable all ...
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IDT82P2282 3.20 FRAME GENERATOR 3.20.1 GENERATION 3.20.1 Mode In T1/J1 mode, the data to be transmitted can be generated as Super-Frame (SF), Extended Super-Frame (ESF), T1 Digital Multiplexer (DM) or Switch Line Carrier - 96 (SLC-96) format. ...
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IDT82P2282 the mimic pattern is the same as the F-bit. The mimic pattern insertion is for diagnostic purpose. The Yellow alarm signal will be manually inserted in the data stream to be transmitted when the XYEL bit is set, or ...
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IDT82P2282 3.20.1.2 E1 Mode In E1 mode, the Frame Generator can generate Basic Frame, CRC-4 Multi-Frame and Channel Associated Signaling (CAS) Multi- Frame. The Frame Generator can also transmit alarm indication signal when special conditions occurs in the received data ...
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IDT82P2282 3.20.1.2.1 Interrupt Summary In E1 mode, the interrupt is summarized in Table 49. When there are conditions meeting the interrupt sources, the corre- sponding Interrupt Indication bit will be set. When the Interrupt Indication Table 49: Interrupt Summary In ...
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IDT82P2282 Table 50: Related Bit / Register In Chapter 3.20.1.2 Bit FDIS GENCRC CRCM SIGEN SiDIS FEBEDIS XDIS FAS1INV FASALLINV NFASINV CRCPINV CASPINV CRCINV Si[1] Si[0] REMAIS AUTOYELLOW G706RAI MFAIS TS16LOS TS16AIS SaX[1:4] (‘X’ is from SaXEN ...
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IDT82P2282 3.20.2 HDLC TRANSMITTER The HDLC Transmitter inserts the data into the selected position to form HDLC packet data stream. 3.20.2.1 HDLC Channel Configuration In T1/J1 mode ESF & formats, three HDLC Transmitters (#1, #2 & #3) per ...
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IDT82P2282 Table 52: Related Bit / Register In Chapter 3.20.2.2 ~ Chapter 3.20.2.4 Bit THDLCM EOM THDLC1 Control / THDLC2 Control / THDLC3 Control ABORT TRST DAT[7:0] THDLC1 Data / THDLC2 Data / THDLC3 Data FUL EMP TFIFO1 Status / ...
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IDT82P2282 3.20.3 AUTOMATIC PERFORMANCE REPORT MESSAGE (T1/ J1 ONLY) The Automatic Performance Report Message (APRM) can only be transmitted in the ESF format in T1/J1 mode. Five kinds of events are counted every second in the APRM: 1. The Bipolar ...
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IDT82P2282 Table 55: Related Bit / Register In Chapter 3.20.3 Bit Register AUTOPRM CRBIT RBIT APRM Control U1BIT U2BIT LBBIT 3.20.4 BIT-ORIENTED MESSAGE TRANSMITTER (T1/J1 ONLY) The Bit Oriented Message (BOM) can only be transmitted in the ESF format in ...
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IDT82P2282 3.21 TRANSMIT BUFFER Transmit Buffer can be used in the circumstances that backplane timing is different from the line side timing in Transmit Slave mode. The function of timing option is also integrated in this block. The source of ...
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IDT82P2282 3.23 TRANSMIT JITTER ATTENUATOR The Transmit Jitter Attenuator of each link can be chosen to be used or not. This selection is made by the TJA_E bit. The Jitter Attenuator consists of a FIFO and a DPLL, as shown ...
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IDT82P2282 3.24 WAVEFORM SHAPER / LINE BUILD OUT According to the various cables, configured by the PULS[3:0] bits, three ways of manipulating the waveform shaper can be selected before the data is transmitted: 1. Preset Waveform Template; 2. Line Build ...
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IDT82P2282 To meet the template, two preset waveform templates are provided corresponding to two kinds of cable impedance. The selection is made by the PULS[3:0] bits. In internal impedance matching mode, if the cable impedance is 75 Ω, the PULS[3:0] ...
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IDT82P2282 Table 62: Transmit Waveform Value For E1 75 Ohm Sample 1 0000000 0000000 Sample 2 0000000 0000000 Sample 3 0000000 0000000 Sample 4 0001100 0000000 Sample 5 0110000 0000000 Sample 6 0110000 0000000 Sample 7 ...
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IDT82P2282 Table 64: Transmit Waveform Value For T1 0~133 Sample 1 0010111 1000010 Sample 2 0100111 1000001 Sample 3 0100111 0000000 Sample 4 0100110 0000000 Sample 5 0100101 0000000 Sample 6 0100101 0000000 Sample 7 ...
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IDT82P2282 Table 66: Transmit Waveform Value For T1 266~399 Sample 1 0011111 1000011 Sample 2 0110001 1000010 Sample 3 0101111 1000001 Sample 4 0101100 0000000 Sample 5 0101011 0000000 Sample 6 0101010 0000000 Sample 7 ...
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IDT82P2282 Table 68: Transmit Waveform Value For T1 533~655 Sample 1 0100000 1000011 Sample 2 0111111 1000010 Sample 3 0111000 1000001 Sample 4 0110011 0000000 Sample 5 0101111 0000000 Sample 6 0101110 0000000 Sample 7 ...
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IDT82P2282 Table 70: Transmit Waveform Value For DS1 0 dB LBO Sample 1 0010111 1000010 Sample 2 0100111 1000001 Sample 3 0100111 0000000 Sample 4 0100110 0000000 Sample 5 0100101 0000000 Sample 6 0100101 0000000 Sample ...
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IDT82P2282 Table 72: Transmit Waveform Value For DS1 -15.0 dB LBO Sample 1 0000000 0110101 Sample 2 0000000 0110011 Sample 3 0000000 0110000 Sample 4 0000001 0101101 Sample 5 0000100 0101010 Sample 6 0001000 0100111 Sample ...
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IDT82P2282 3.25 LINE DRIVER The Line Driver can be set to High-Z for redundant application. The following ways will set the drivers to High-Z: 1. Setting the THZ pin to high will globally set both the Line Drivers to High-Z; ...
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IDT82P2282 3.26 TRANSMITTER IMPEDANCE MATCHING In T1/J1 mode, the transmitter impedance matching can be real- ized by using internal impedance matching circuit. 100 Ω, 110 Ω, 75 Ω or 120 Ω internal impedance matching circuit can be selected by the ...
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IDT82P2282 3.27 TESTING AND DIAGNOSTIC FACILITIES 3.27.1 PRBS GENERATOR / DETECTOR The PRBS Generator / Detector generates test pattern to either the transmit or receive direction, and detects the pattern in the opposite direction. The direction is determined by the ...
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IDT82P2282 3.27.2 LOOPBACK System Loopback, Payload Loopback, Local Digital Loopback 1 & 2, Remote Loopback and Analog Loopback are all supported in the IDT82P2282. Their routes are shown in the Functional Block Diagram. 3.27.2.1 System Loopback The System Loopback can ...
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IDT82P2282 TSD1 / MTSD TSIG1 / MTSIG Transmit System TSFS1 / MTSFS Interface TSCK1 / MTSCK RSCK1 / MRSCK RSFS1 / MRSFS Receive System RSIG1 / MRSIG Interface RSD1 / MRSD TSD2 TSIG2 Transmit System Interface TSFS2 TSCK2 RSCK2 RSFS2 ...
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IDT82P2282 Table 78: Related Bit / Register In Chapter 3.27.2 & Chapter 3.27.3 Bit SRLP SLLP DLLP RLP DLP ALP GSUBST[2:0] SUBST[2:0] MON3 MON0 Note means Indirect Register in the Transmit Payload Control function block. DUAL T1/E1/J1 LONG ...
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IDT82P2282 3.28 INTERRUPT SUMMARY When the INT pin is asserted low, it means at least one interrupt has occurred in the device. Reading the Timer Interrupt Indication regis- ter and Interrupt Requisition Link ID register will find whether the timer ...
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IDT82P2282 4 OPERATION 4.1 POWER-ON SEQUENCE To power on the device, the following sequence should be followed: 1. Apply ground; 2. Apply 3 Apply 1.8 V. 4.2 RESET When the device is powered-up, all the registers contain random ...
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IDT82P2282 4.4 MICROPROCESSOR INTERFACE The microprocessor interface provides access to read and write the registers in the device. The interface consists of Serial Peripheral Inter- face (SPI) and parallel microprocessor interface SCLK Instruction SDI ...
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IDT82P2282 4.4.2 PARALLEL MICROPROCESSOR INTERFACE Pull the SPIEN pin to low, the microprocessor interface will be set in parallel mode. In this mode, the interface is compatible with the Motorola and the Intel microprocessor, which is selected by the MPM ...
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IDT82P2282 4.5 INDIRECT REGISTER ACCESS SCHEME In Receive CAS/RBS Buffer, Receive Payload Control and Trans- mit Payload Control blocks, per-channel/per-timeslot indirect register is accessed by using an indirect register access scheme. 4.5.1 INDIRECT REGISTER READ ACCESS The indirect register read ...
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IDT82P2282 5 PROGRAMMING INFORMATION 5.1 REGISTER MAP In the ‘Reg’ column, the ‘X’ represents corresponding to the two links. 5.1.1 T1/J1 MODE 5.1.1.1 Direct Register T1/J1 Reg Bit 7 Bit 6 Bit 5 (Hex) 000 ID7 ID6 ...
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IDT82P2282 T1/J1 Reg Bit 7 Bit 6 Bit 5 (Hex) X34 - DAC_IE TJA_IE X35 - - X36 - - X37 - - X38 - TJITT6 TJITT5 X39 - RJITT6 RJITT5 X3A - - X3B - DAC_IS TJA_IS X3C CNTH[7] ...
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IDT82P2282 T1/J1 Reg Bit 7 Bit 6 Bit 5 (Hex) X68 ~ X6A - - X6B - - X6C - - X6D - - X6E - - X6F - - X70 - - X71 - - X72 - - X73 ...
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IDT82P2282 T1/J1 Reg Bit 7 Bit 6 Bit 5 (Hex) X98 DAT7 DAT6 DAT5 X99 DAT7 DAT6 DAT5 X9A DAT7 DAT6 DAT5 X9B - - X9C - - X9D - - X9E - - X9F - - XA0 - - ...
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IDT82P2282 T1/J1 Reg Bit 7 Bit 6 Bit 5 (Hex) XC7 - - XC8 - - XC9 RWN ADDRESS ADDRESS 6 XCA D7 D6 XCB SIGSNAP GSTRKEN ZCS2 XCC - - XCD - - XCE RWN ADDRESS ADDRESS 6 XCF ...
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IDT82P2282 5.1.1.2 Indirect Register PMON Address (Hex) Bit 7 Bit 6 00 CRCE7 CRCE6 CRCE5 FER7 FER6 PRGD7 PRGD6 PRGD5 07 PRGD15 PRGD14 PRGD13 08 LCV7 ...
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IDT82P2282 5.1.2 E1 MODE 5.1.2.1 Direct Register E1 Reg Bit 7 Bit 6 Bit 5 (Hex) 000 ID7 ID6 ID5 001 ~ - - - 003 004 - - - 005 - - - 006 - - - 007 - ...
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IDT82P2282 E1 Reg Bit 7 Bit 6 Bit 5 (Hex) X38 - TJITT6 TJITT5 X39 - RJITT6 RJITT5 X3A - - - X3B - DAC_IS TJA_IS X3C CNTH[7] CNTH[6] CNTH[5] X3D CNTL[7] CNTL[6] CNTL[5] X3E - - - X3F - ...
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IDT82P2282 E1 Reg Bit 7 Bit 6 Bit 5 (Hex) X64 - - - X65 - - - X66 - - - X67 - - - X68 - - - X69 - - - X6A - - - X6B - ...
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IDT82P2282 E1 Reg Bit 7 Bit 6 Bit 5 (Hex) X9B - - - X9C - - - X9D - - - X9E - - - X9F - - - XA0 - - - XA1 HA7 HA6 HA5 XA2 HA7 ...
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IDT82P2282 E1 Reg Bit 7 Bit 6 Bit 5 (Hex) XCD - - - XCE RWN ADDRESS6 ADDRESS5 ADDRESS4 ADDRESS3 ADDRESS2 ADDRESS1 ADDRESS0 RPLC Access Control XCF XD0 SIGSNAP GSTRKEN - XD1 - - - XD2 - ...
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IDT82P2282 5.1.2.2 Indirect Register PMON Address (Hex) Bit 7 Bit 6 00 CRCE7 CRCE6 CRCE5 FER7 FER6 PRGD7 PRGD6 PRGD5 07 PRGD15 PRGD14 PRGD13 PRGD12 08 ...
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IDT82P2282 TPLC Address (Hex) Bit 7 Bit 6 Bit SUBST2 SUBST1 SUBST0 DTRK7 DTRK6 DTRK5 TEST TEST Programming Information DUAL T1/E1/J1 LONG HAUL / SHORT ...
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IDT82P2282 5.2 REGISTER DESCRIPTION Depending on the operating mode, the registers are configured for T1/J1 or E1. Before setting any other registers, the operating mode should be selected in registers 020H and 120H. According to the access method, the registers ...
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IDT82P2282 5.2.1 T1/J1 MODE 5.2.1.1 Direct Register T1/J1 Chip ID For Dual Transceiver (000H) Bit No. 7 Bit Name ID7 Type R Default 0 ID[7:0]: The ID[7:0] bits are pre-set. The ID[7:4] bits represent the IDT82P2282 device. The ID[3:0] bits ...
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IDT82P2282 T1/J1 G.772 Monitor Control (005H) Bit No Bit Name Type Default MON[3], MON[0]: These bits determine whether the G.772 Monitor is implemented. When the G.772 Monitor is implemented, these bits select one transmitter or receiver to be ...
Page 128
IDT82P2282 T1/J1 GPIO Control (006H) Bit No. 7 Bit Name Type Default LEVEL[0]: When the GPIO[0] pin is defined as an output port, this bit can be read and written The GPIO[0] pin outputs low level ...
Page 129
IDT82P2282 T1/J1 Reference Clock Output Select (007H) Bit No Bit Name Type Default RO20: This bit selects the recovered clock from the line side of one link to be internally looped to the REFB_OUT output pin ...
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IDT82P2282 T1/J1 Interrupt Requisition Link ID (009H) Bit No. 7 Bit Name Type Default INTn interrupt is generated in the corresponding link least one interrupt is generated in the corresponding link. T1/J1 Timer Interrupt ...
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IDT82P2282 T1/J1 PMON Access Port (00EH) Bit No. 7 Bit Name Type Reserved Default LINKSEL0: This bit selects one of the two links. One of the PMON indirect registers of the selected link can be accessed by the microprocessor. = ...
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IDT82P2282 T1/J1 Backplane Global Configuration (010H) Bit No. 7 Bit Name Type Reserved Default RSLVCK: This bit is valid when both two links are in the Receive Clock Slave mode Each link uses its own clock signal on ...
Page 133
IDT82P2282 T1/J1 Transmit Jitter Attenuation Configuration (021H, 121H) Bit No. 7 Bit Name Type Reserved Default TJITT_TEST The real time interval between the read and write pointer of the FIFO is indicated in the TJITT[6:0] bits (b6~0, T1/J1-038H,...). ...
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IDT82P2282 T1/J1 Transmit Configuration 0 (022H, 122H) Bit No. 7 Bit Name Type Reserved Default T_OFF The transmit path is power up The transmit path is power down. The Line Driver is in high impedance. T_MD: ...
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IDT82P2282 T1/J1 Transmit Configuration 1 (023H, 123H) Bit No. 7 Bit Name Type Reserved Default DFM_ON The Driver Failure Monitor is disabled The Driver Failure Monitor is enabled. T_HZ The Line Driver works normally. ...
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IDT82P2282 T1/J1 Transmit Configuration 2 (024H, 124H) Bit No. 7 Bit Name Type Reserved Default SCAL[5:0]: The following setting lists the standard values of normal amplitude in different operating modes. Each step change (one increasing or decreasing from the standard ...
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IDT82P2282 T1/J1 Transmit Configuration 3 (025H, 125H) Bit No Bit Name DONE RW Type R/W R/W Default 0 0 This register is valid when the PULS[3:0] bits (b3~0, T1/J1-023H,...) are set to ‘11xx’. DONE Disable the ...
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IDT82P2282 T1/J1 Transmit Configuration 4 (026H, 126H) Bit No Bit Name WDAT6 Type Reserved R/W Default 0 WDAT[6:0]: These bits contain the data to be stored in the pulse template RAM which is addressed by the UI[1:0] bits ...
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IDT82P2282 T1/J1 Receive Configuration 0 (028H, 128H) Bit No. 7 Bit Name Type Reserved Default R_OFF The receive path is power up The receive path is power down. R_MD: This bit selects the line code rule ...
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IDT82P2282 T1/J1 Receive Configuration 1 (029H, 129H) Bit No Bit Name EQ_ON Type Reserved R/W Default 0 EQ_ON The Equalizer is off in short haul applications The Equalizer long haul applications. ...
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IDT82P2282 T1/J1 Receive Configuration 2 (02AH, 12AH) Bit No Bit Name Type Reserved Default SLICE[1:0]: These two bits define the Data Slicer threshold. = 00: The Data Slicer generates a mark if the voltage on the RTIPn/RRINGn pins ...
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IDT82P2282 T1/J1 Maintenance Function Control 0 (02BH, 12BH) Bit No Bit Name DLLP Type Reserved R/W Default 0 DLLP Disable the Local Digital Loopback Enable the Local Digital Loopback 1. SLLP ...
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IDT82P2282 T1/J1 Maintenance Function Control 1 (02CH, 12CH) Bit No Bit Name Type Default LAC: This bit selects the LOS criterion The T1.231 is selected. In short haul application, the LOS is declared when the incoming ...
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IDT82P2282 T1/J1 Maintenance Function Control 2 (031H, 131H) Bit No Bit Name BPV_INS Type Reserved R/W Default 0 BPV_INS: A transition from ‘0’ to ‘1’ on this bit generates a single Bipolar Violation (BPV) Error to be inserted ...
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IDT82P2282 T1/J1 Transmit And Receive Termination Configuration (032H, 132H) Bit No Bit Name Type Reserved Default T_TERM[2:0]: These bits select the internal impedance of the transmit path to match the cable impedance: = 000: The 75 Ω internal ...
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IDT82P2282 T1/J1 Interrupt Enable Control 1 (034H, 134H) Bit No Bit Name DAC_IE Type Reserved R/W Default 0 DAC_IE Disable the interrupt on the INT pin when the DAC_IS bit (b6, T1/J1-03BH,...) is ‘1’ ...
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IDT82P2282 T1/J1 Interrupt Trigger Edges Select (035H, 135H) Bit No Bit Name Type Default DF_IES The DF_IS bit (b2, T1/J1-03AH,...) will be set to ‘1’ when there is a transition from ‘0’ to ‘1’ on the ...
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IDT82P2282 T1/J1 Line Status Register 1 (037H, 137H) Bit No Bit Name Type Reserved Default LATT[4:0]: These bits indicate the current gain of the VGA relative peak pulse level. LATT[4:0] 00000 00001 00010 00011 00100 ...
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IDT82P2282 T1/J1 Transmit Jitter Measure Value Indication (038H, 138H) Bit No Bit Name TJITT6 Type Reserved R Default 0 TJITT[6:0]: When the TJITT_TEST bit (b5, T1/J1-021H,...) is ‘0’, these bits represent the current interval between the read and ...
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IDT82P2282 T1/J1 Interrupt Status 0 (03AH, 13AH) Bit No Bit Name Type Default DF_IS There is no status change on the DF_S bit (b2, T1/J1-036H,...). = 1: When the DF_IES bit (b2, T1/J1-035H,...) is ‘0’, the ...
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IDT82P2282 T1/J1 Interrupt Status 1 (03BH, 13BH) Bit No Bit Name DAC_IS Type Reserved R Default 0 DAC_IS The sum of a pulse template does not exceed the D/A limitation (+63) when more than one UI ...
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IDT82P2282 T1/J1 EXZ Error Counter H-Byte (03CH, 13CH) Bit No Bit Name CNTH[7] CNTH[6] Type R R Default 0 0 CNTH[7:0]: These bits, together with the CNTL[7:0] bits, reflect the content in the internal 16-bit EXZ counter. T1/J1 ...
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IDT82P2282 T1/J1 Interrupt Module Indication 2 (03FH, 13FH) Bit No Bit Name Type Default LIU interrupt is generated in the Receive / Transmit Internal Termination, Adaptive Equalizer, Data Slicer, CLK&Data Recovery, Receive / Transmit Jitter ...
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IDT82P2282 T1/J1 Interrupt Module Indication 0 (040H, 140H) Bit No Bit Name IBCD RBOC Type R R Default 0 0 IBCD interrupt is generated in the Inband Loopback Code Detector function block Interrupt ...
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IDT82P2282 T1/J1 Interrupt Module Indication 1 (041H, 141H) Bit No Bit Name THDLC3 THDLC2 Type R R Default 0 0 THDLC3 interrupt is generated in the HDLC Transmitter #3 function block Interrupt is ...
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IDT82P2282 T1/J1 TBIF Option Register (042H, 142H) Bit No Bit Name Type Reserved Default FBITGAP: This bit is valid in Transmit Clock Master mode The F-bit is not gapped The F-bit is gapped (no ...
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IDT82P2282 T1/J1 TBIF Operating Mode (043H, 143H) Bit No Bit Name Type Default MAP[1:0]: In Transmit Clock Slave mode and Transmit Multiplexed mode, these 2 bits select the T1/ format mapping schemes. MAP[1:0] Note: * These ...
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IDT82P2282 T1/J1 TBIF TS Offset (044H, 144H) Bit No Bit Name TSOFF6 Type Reserved R/W Default 0 TSOFF[6:0]: These bits give a binary number to define the channel offset. The channel offset is between the framing pulse on ...
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IDT82P2282 T1/J1 RBIF Option Register (046H, 146H) Bit No Bit Name Type Reserved Default FBITGAP: This bit is valid in Receive Clock Master mode The F-bit is not gapped The F-bit is gapped (no ...
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IDT82P2282 T1/J1 RBIF Mode (047H, 147H) Bit No Bit Name Type Default MAP[1:0]: In Receive Clock Slave mode and Receive Multiplexed mode, these 2 bits select the T1/ format mapping schemes. MAP[1:0] Note: * These 2 ...
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IDT82P2282 T1/J1 RBIF Frame Pulse (048H, 148H) Bit No Bit Name Type Reserved Default FSINV The receive framing pulse RSFSn is active high The receive framing pulse RSFSn is active low. In Receive Multiplexed ...
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IDT82P2282 T1/J1 RBIF TS Offset (049H, 149H) Bit No Bit Name TSOFF6 Type Reserved R/W Default 0 TSOFF[6:0]: These bits give a binary number to define the channel offset. The channel offset is between the framing pulse on ...
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IDT82P2282 T1/J1 RTSFS Change Indication (04BH, 14BH) Bit No Bit Name Type Default RCOFAI: This bit is valid in Receive Clock Slave mode and Receive Multiplexed mode The interval of the pulses on the RSFSn/MRSFS pin ...
Page 164
IDT82P2282 T1/J1 FRMR Mode 0 (04DH, 14DH) Bit No Bit Name Type Default UNFM The data stream is received in framed mode and is processed by the Frame Processor The data stream is received ...
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IDT82P2282 T1/J1 FRMR Mode 1 (04EH, 14EH) Bit No Bit Name Type Default DDSC: This bit selects the synchronization criteria format correct DDS pattern is received before the first F-bit of ...
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IDT82P2282 T1/J1 FRMR Status (04FH, 14FH) Bit No Bit Name Type Default OOFV The SF/ESF/T1 DM/SLC-96 frame is in synchronization The frame is out of synchronization. T1/J1 FRMR Interrupt Control 0 (050H, 150H) Bit ...
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IDT82P2282 T1/J1 FRMR Interrupt Control 1 (051H, 151H) Bit No Bit Name Type Reserved Default RMFBE Disable the interrupt on the INT pin when the RMFBI bit (b4, T1/J1-053H,...) is ‘1’ Enable the interrupt ...
Page 168
IDT82P2282 T1/J1 FRMR Interrupt Indication 0 (052H, 152H) Bit No Bit Name Type Reserved Default EXCRCERI: In ESF format, once the accumulated CRC-6 errors exceed 319 (>319 second fixed window, an excessive CRC-6 error event ...
Page 169
IDT82P2282 T1/J1 FRMR Interrupt Indication 1 (053H, 153H) Bit No Bit Name Type Reserved Default RMFBI The received bit is not the first bit of each SF/ESF/T1 DM/SLC-96 frame The first bit of each ...
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IDT82P2282 COFAI The F bit position is not changed The new-found F bit position differs from the previous one. This bit will be cleared if a ’1’ is written to it. T1/J1 RDL0 (056H, 156H) Bit ...
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IDT82P2282 T1/J1 RDL2 (058H, 158H) Bit No Bit Name Type Reserved Default S[4:1]: In SLC-96 format, these bits reflect the content in the Switch bits. The S[1] bit is the LSB. In de-bounce condition, these bits are updated ...
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IDT82P2282 T1/J1 DLB Interrupt Control (05CH, 15CH) Bit No Bit Name Type Reserved Default SCDEB Disable the de-bounce function of the overhead extraction Enable the de-dounce function of the overhead extraction. SCAE ...
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IDT82P2282 T1/J1 DLB Interrupt Indication (05DH, 15DH) Bit No Bit Name Type Default SCAI The value in the A[2:1] bits is not changed The value in the A[2:1] bits is changed. SCSI ...
Page 174
IDT82P2282 T1/J1 Mode (062H, 162H) Bit No Bit Name Type Default FDLBYP: In ESF format, this bit is valid when the FDIS bit (b0, T1/J1-062H,...) is ‘0’ Enable the DL bit position to be replaced by ...
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IDT82P2282 T1/J1 XDL0 (065H, 165H) Bit No Bit Name C8 C7 Type R R Default 0 0 C[8:1]: These bits, together with the C[11:9] bits (b2~0, T1/J1-066H,...), are valid in SLC-96 format when the FDIS bit (b0, T1/J1-062H,...) ...
Page 176
IDT82P2282 T1/J1 XDL2 (067H, 167H) Bit No Bit Name Type Reserved Default S[4:1]: These bits are valid in SLC-96 format when the FDIS bit (b0, T1/J1-062H,...) and the FDLBYP bit (b2, T1/J1-062H,...) are both ‘0’s. They contain the ...
Page 177
IDT82P2282 T1/J1 FGEN Maintenance 1 (06CH, 16CH) Bit No Bit Name Type Default MIMICEN: This bit is valid when the FDIS bit (b0, T1/J1-062H,...) is ‘0’ Disable the mimic pattern insertion The mimic pattern ...
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IDT82P2282 T1/J1 FGEN Interrupt Control (06DH, 16DH) Bit No Bit Name Type Default MFE Disable the interrupt on the INT pin when the MFI bit (b1, T1/J1-06EH,...) is ‘1’ Enable the interrupt on the ...
Page 179
IDT82P2282 T1/J1 Error Insertion (06FH, 16FH) Bit No Bit Name Type Default DDSINV: This bit is valid format when the FDIS bit (b0, T1/J1-062H,...) is ‘0’. A transition from ‘0’ to ‘1’ on this bit ...
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IDT82P2282 T1/J1 Transmit Timing Option (070H, 170H) Bit No Bit Name Type Default XTS: In Transmit Clock Master mode The source of the transmit clock is selected from the clock generated by the internal clock generator ...
Page 181
IDT82P2282 T1/J1 PRGD Status/Error Control (072H, 172H) Bit No Bit Name Type Default BERE Disable the interrupt on the INT pin when the BERI bit (b3, T1/J1-073H,...) is ‘1’ Enable the interrupt on the ...
Page 182
IDT82P2282 T1/J1 XIBC Control (074H, 174H) Bit No Bit Name Type Default IBCDEN Disable transmitting the inband loopback code Enable transmitting the inband loopback code. IBCDUNFM The inband loopback code is transmitted ...
Page 183
IDT82P2282 T1/J1 IBCD Detector Configuration (076H, 176H) Bit No Bit Name Type Reserved Default IBCDIDLE The F-bit is compared with the target activate/deactivate inband loopback code, but the result of the F-bit comparison is discarded. = ...
Page 184
IDT82P2282 T1/J1 IBCD Detector Status (077H, 177H) Bit No Bit Name Type Default LBA The activate code is loss. That is, more than 600 bits are not matched with the target activate inband loopback code in ...
Page 185
IDT82P2282 T1/J1 IBCD Interrupt Control (07AH, 17AH) Bit No Bit Name Type Default LBAE Disable the interrupt on the INT pin when the LBAI bit (b1, T1/J1-07BH,...) is ‘1’ Enable the interrupt on the ...
Page 186
IDT82P2282 T1/J1 ELST Configuration (07CH, 17CH) Bit No Bit Name Type Default TRKEN: In Receive Clock Slave mode and Receive Multiplexed mode out of synchronization, the trunk code programmed in the TRKCODE[7:0] bits (b7~0, T1/J1-07EH,...) ...
Page 187
IDT82P2282 T1/J1 APRM Control (07FH, 17FH) Bit No Bit Name Type Reserved Default LBBIT: This bit is valid in ESF format when the AUTOPRM bit (b0, T1/J1-07FH,...) is ‘1’. The value in this bit will be transmitted in ...
Page 188
IDT82P2282 T1/J1 XBOC Code (080H, 180H) Bit No Bit Name Type Reserved Default XBOC[5:0]: These bits are only valid in the ESF format. When the XBOC[5:0] bits are written with any 6-bit code other than the ‘111111’, the ...
Page 189
IDT82P2282 T1/J1 BOC Interrupt Indication (082H, 182H) Bit No Bit Name Type Default BOCI The BOC[5:0] bits (b5~0, T1/J1-083H,...) are not updated The BOC[5:0] bits (b5~0, T1/J1-083H,...) are updated. This bit will be cleared ...
Page 190
IDT82P2282 T1/J1 THDLC Enable Control (084H, 184H) Bit No Bit Name Type Default TDLEN3 All the functions of the HDLC Transmitter #3 is disabled All the functions of the HDLC Transmitter #3 is enabled. ...
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IDT82P2282 T1/J1 THDLC2 Assignment (086H, 186H) Bit No Bit Name EVEN Type Reserved R/W Default 0 T1/J1 THDLC3 Assignment (087H, 187H) Bit No Bit Name EVEN Type Reserved R/W Default 0 The function of the above ...
Page 192
IDT82P2282 T1/J1 THDLC2 Bit Select (089H, 189H) Bit No Bit Name BITEN7 BITEN6 Type R/W R/W Default 0 0 T1/J1 THDLC3 Bit Select (08AH, 18AH) Bit No Bit Name BITEN7 BITEN6 Type R/W R/W Default 0 ...
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IDT82P2282 T1/J1 RHDLC Enable Control (08BH, 18BH) Bit No Bit Name Type Default RDLEN3 All the functions of the HDLC Receiver #3 is disabled All the functions of the HDLC Receiver #3 is enabled. ...
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IDT82P2282 T1/J1 RHDLC2 Assignment (08DH, 18DH) Bit No Bit Name EVEN Type Reserved R/W Default 0 T1/J1 RHDLC3 Assignment (08EH, 18EH) Bit No Bit Name EVEN Type Reserved R/W Default 0 The function of the above ...
Page 195
IDT82P2282 T1/J1 RHDLC2 Bit Select (090H, 190H) Bit No Bit Name BITEN7 BITEN6 Type R/W R/W Default 0 0 T1/J1 RHDLC3 Bit Select (091H, 191H) Bit No Bit Name BITEN7 BITEN6 Type R/W R/W Default 0 ...
Page 196
IDT82P2282 T1/J1 RHDLC1 Control Register (092H, 192H) Bit No Bit Name Type Default T1/J1 RHDLC2 Control Register (093H, 193H) Bit No Bit Name Type Default T1/J1 RHDLC3 Control Register (094H, 194H) Bit No Bit ...
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IDT82P2282 RRST: A transition from ‘0’ to ‘1’ on this bit resets the corresponding HDLC Receiver. The reset will clear the FIFO, the PACK bit (b0, T1/J1-095H,... / 096H,... / 097H,...) and the EMP bit (b1, T1/J1-095H,... / 096H,... / ...
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IDT82P2282 T1/J1 RHDLC1 Data (098H, 198H) Bit No Bit Name DAT7 DAT6 Type R R Default 0 0 T1/J1 RHDLC2 Data (099H, 199H) Bit No Bit Name DAT7 DAT6 Type R R Default 0 0 T1/J1 ...
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IDT82P2282 T1/J1 RHDLC1 Interrupt Control (09BH, 19BH) Bit No Bit Name Type Default T1/J1 RHDLC2 Interrupt Control (09CH, 19CH) Bit No Bit Name Type Default T1/J1 RHDLC3 Interrupt Control (09DH, 19DH) Bit No Bit ...
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IDT82P2282 T1/J1 RHDLC1 Interrupt Indication (09EH, 19EH) Bit No Bit Name Type Default T1/J1 RHDLC2 Interrupt Indication (09FH, 19FH) Bit No Bit Name Type Default T1/J1 RHDLC3 Interrupt Indication (0A0H, 1A0H) Bit No Bit ...