82P2282PF IDT, Integrated Device Technology Inc, 82P2282PF Datasheet - Page 361

• Manufacturer Part Number: 82P2282PF
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82P2282PF

• Screening Level: Industrial
• Pin Count: 100
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

IDT82P2282
6.3
Figure - 42 shows its state diagram. A description of each state is listed
in Table 85. Note that the figure contains two main branches to access
Table 85: TAP Controller State Description
IEEE STD 1149.1 JTAG Test Access Port
Select-DR-
Update-DR The Boundary Scan Register is provided with a latched parallel output to prevent changes while data is shifted in response to the EXTEST and SAM-
Capture-IR In this controller state, the shift register contained in the instruction register loads a fixed value of '100' on the rising edge of TCK. This supports fault-iso-
Pause-DR The pause state allows the test controller to temporarily halt the shifting of data through the test data register in the serial path between TDI and TDO.
Test Logic
Select-IR-
Run-Test/
Exit1-DR This is a temporary state. While in this state, if TMS is held high, a rising edge applied to TCK causes the controller to enter the Update-DR state, which
Exit2-DR This is a temporary state. While in this state, if TMS is held high, a rising edge applied to TCK causes the controller to enter the Update-DR state, which
Capture-
Shift-DR In this controller state, the test data register connected between TDI and TDO as a result of the current instruction shifts data on stage toward its serial
Exit1-IR
Shift-IR
Reset
State
Scan
Scan
Idle
DR
The TAP controller is a 16-state synchronous state machine.
TEST ACCESS PORT CONTROLLER
In this state, the test logic is disabled to continue normal operation of the device. During initialization, the device initializes the instruction register with the
IDCODE instruction.
Regardless of the original state of the controller, the controller enters the Test-Logic-Reset state when the TMS input is held high for at least 5 rising
edges of TCK. The controller remains in this state while TMS is high.
This is a controller state between scan operations. Once in this state, the controller remains in the state as long as TMS is held low. The instruction reg-
ister and all test data registers retain their previous state. When TMS is high and a rising edge is applied to TCK, the controller moves to the Select-DR
state.
This is a temporary controller state and the instruction does not change in this state. The test data register selected by the current instruction retains its
previous state. If TMS is held low and a rising edge is applied to TCK when in this state, the controller moves into the Capture-DR state and a scan
sequence for the selected test data register is initiated. If TMS is held high and a rising edge applied to TCK, the controller moves to the Select-IR-Scan
state.
In this state, the Boundary Scan Register captures input pin data if the current instruction is EXTEST or SAMPLE/PRELOAD. The instruction does not
change in this state. The other test data registers, which do not have parallel input, are not changed. When the TAP controller is in this state and a rising
edge is applied to TCK, the controller enters the Exit1-DR state if TMS is high or the Shift-DR state if TMS is low.
output on each rising edge of TCK. The instruction does not change in this state. When the TAP controller is in this state and a rising edge is applied to
TCK, the controller enters the Exit1-DR state if TMS is high or remains in the Shift-DR state if TMS is low.
terminates the scanning process. If TMS is held low and a rising edge is applied to TCK, the controller enters the Pause-DR state. The test data register
selected by the current instruction retains its previous value and the instruction does not change during this state.
For example, this state could be used to allow the tester to reload its pin memory from disk during application of a long test sequence. The test data reg-
ister selected by the current instruction retains its previous value and the instruction does not change during this state. The controller remains in this
state as long as TMS is low. When TMS goes high and a rising edge is applied to TCK, the controller moves to the Exit2-DR state.
terminates the scanning process. If TMS is held low and a rising edge is applied to TCK, the controller enters the Shift-DR state. The test data register
selected by the current instruction retains its previous value and the instruction does not change during this state.
PLE/PRELOAD instructions. When the TAP controller is in this state and the Boundary Scan Register is selected, data is latched into the parallel output
of this register from the shift-register path on the falling edge of TCK. The data held at the latched parallel output changes only in this state. All shift-reg-
ister stages in the test data register selected by the current instruction retain their previous value and the instruction does not change during this state.
This is a temporary controller state. The test data register selected by the current instruction retains its previous state. If TMS is held low and a rising
edge is applied to TCK when in this state, the controller moves into the Capture-IR state, and a scan sequence for the instruction register is initiated. If
TMS is held high and a rising edge is applied to TCK, the controller moves to the Test-Logic-Reset state. The instruction does not change during this
state.
lation of the board-level serial test data path. Data registers selected by the current instruction retain their value and the instruction does not change dur-
ing this state. When the controller is in this state and a rising edge is applied to TCK, the controller enters the Exit1-IR state if TMS is held high, or the
Shift-IR state if TMS is held low.
In this state, the shift register contained in the instruction register is connected between TDI and TDO and shifts data one stage towards its serial output
on each rising edge of TCK. The test data register selected by the current instruction retains its previous value and the instruction does not change dur-
ing this state. When the controller is in this state and a rising edge is applied to TCK, the controller enters the Exit1-IR state if TMS is held high, or
remains in the Shift-IR state if TMS is held low.
This is a temporary state. While in this state, if TMS is held high, a rising edge applied to TCK causes the controller to enter the Update-IR state, which
terminates the scanning process. If TMS is held low and a rising edge is applied to TCK, the controller enters the Pause-IR state. The test data register
selected by the current instruction retains its previous value and the instruction does not change during this state.
361
Description
either the data or instruction registers. The value shown next to each
state transition in this figure states the value present at TMS at each ris-
ing edge of TCK.
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
August 20, 2009