82P2282PF IDT, Integrated Device Technology Inc, 82P2282PF Datasheet - Page 17

• Manufacturer Part Number: 82P2282PF
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82P2282PF

• Screening Level: Industrial
• Pin Count: 100
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

IDT82P2282
Pin Description
TSCK[1] / MTSCK
TSFS[1] / MTSFS
TSIG[1] / MTSIG
TSCK[2]
TSFS[2]
TSIG[2]
Name
OSCI
Output / Input
Output / Input
Type
Input
Input
Pin No.
74
66
73
65
76
68
95
TSIG[1:2]: Transmit Side System Signaling for Link 1 ~ 2
The signaling bits are input on these pins. They are located in the lower nibble (b5 ~ b8) and are channel/timeslot-
aligned with the data input on the corresponding TSDn pin.
In Transmit Clock Master mode, TSIGn is sampled on the active edge of the corresponding TSCKn.
In Transmit Clock Slave mode, selected by the TSLVCK bit (b1, T1/J1-010H / b1, E1-010H), TSIGn is sampled on the
active edge of the corresponding TSCKn or both two TSIGn are updated on the active edge of TSCK[1].
MTSIG: Multiplexed Transmit Side System Signaling for Link 1 ~ 2
In Transmit Multiplexed mode, the MTSIG pin is used to input the signaling bits. The signaling bits are located in the
lower nibble (b5 ~ b8) and are channel/timeslot-aligned with the data input on the MTSD pin. Using the byte-interleaved
multiplexing scheme, the MTSIG pin inputs the signaling bits for Link 1 and Link 2. The signaling bits on the MTSIG pin
is sampled on the active edge of MTSCK.
TSIG[1]/MTSIG is a Schmitt-triggered input. TSIG[2] is a Schmitt-triggered input with pull-up resistor.
TSFS[1:2]: Transmit Side System Frame Pulse for Link 1 ~ 2
In T1/J1 Transmit Clock Master mode, TSFSn outputs the pulse to indicate each F-bit or the first F-bit of every SF/ESF/
T1 DM/SLC-96 multi-frame.
In T1/J1 Transmit Clock Slave mode, TSFSn inputs the pulse to indicate each F-bit or the first F-bit of every SF/ESF/T1
DM/SLC-96 multi-frame.
In E1 Transmit Clock Master mode, TSFSn outputs the pulse to indicate the Basic frame, CRC Multi-frame and/or Sig-
naling Multi-frame.
In E1 Transmit Clock Slave mode, TSFSn inputs the pulse to indicate the Basic frame, CRC Multi-frame and/or Signal-
ing Multi-frame.
TSFSn is updated/sampled on the active edge of the corresponding TSCKn. The active polarity of TSFSn is selected
by the FSINV bit (b1, T1/J1-042H,... / b1, E1-042H,...).
MTSFS: Multiplexed Transmit Side System Frame Pulse for Link 1 ~ 2
In T1/J1 Transmit Multiplexed mode, MTSFS inputs the pulse to indicate each F-bit or the first F-bit of every SF/ESF/T1
DM/SLC-96 multi-frame of one link on the multiplexed data bus.
In E1 Transmit Multiplexed mode, MTSFS inputs the pulse to indicate each Basic frame, CRC Multi-frame and/or Sig-
naling Multi-frame of one link on the multiplexed data bus.
MTSFS is sampled on the active edge of MTSCK. The active polarity of MTSFS is selected by the FSINV bit (b1, T1/
J1-042H,... / b1, E1-042H,...).
TSFS[1:2]/MTSFS are Schmitt-triggered inputs/outputs with pull-up resistors.
TSCK[1:2]: Transmit Side System Clock for Link 1 ~ 2
In Transmit Clock Master mode, TSCKn outputs a (gapped) 1.544 MHz (for T1/J1 mode) / 2.048 MHz (for E1 mode)
clock used to sample the signal on the corresponding TSDn and TSIGn pins and update the signal on the correspond-
ing TSFSn pin.
In Transmit Clock Slave mode, TSCKn inputs a 1.544 MHz (for T1/J1 mode only), 2.048 MHz or 4.096 MHz clock used
to sample the signal on the corresponding TSDn, TSIGn and TSFSn pins. Selected by the TSLVCK bit (b1, T1/J1-010H
/ b1, E1-010H), the TSCK[1] can be used for both two links.
MTSCK: Multiplexed Transmit Side System Clock for Link 1 ~ 2
In Transmit Multiplexed mode, MTSCK inputs a 8.192 MHz or 16.384 MHz clock used to sample the signal on the
MTSD, MTSIG and MTSFS pins.
TSCK[1:2]/MTSCK are Schmitt-triggered inputs/outputs with pull-up resistors.
OSCI: Crystal Oscillator Input
This pin is connected to an external clock source.
The clock frequency of OSCI is defined by CLK_SEL[2:0]. The clock accuracy should be ±32 ppm and duty cycle
should be from 40% to 60%.
Hardware or software reset can only be applied when the clock on this pin is available.
Clock Generator
17
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Description
August 20, 2009