82P2282PF IDT, Integrated Device Technology Inc, 82P2282PF Datasheet - Page 103

• Manufacturer Part Number: 82P2282PF
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82P2282PF

• Screening Level: Industrial
• Pin Count: 100
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

3.27
3.27.1
transmit or receive direction, and detects the pattern in the opposite
direction. The direction is determined by the PRBSDIR bit. The pattern
can be generated or detected in unframed mode, in 8-bit-based mode or
in 7-bit-based mode. This selection is made by the PRBSMODE[1:0]
bits. In unframed mode, all the data streams are extracted or replaced
and the per-channel/per-TS configuration in the TEST bit is ignored. In
8-bit-based mode or in 7-bit-based mode, the extracted or replaced
channel/timeslot is specified by the TEST bit. (In 7-bit-based mode, only
the higher 7 bits of the selected channel/timeslot are used for PRBS
test).
3.27.1.1
tern per O.152 and 2
the PATS[1:0] bits.
to ‘1’ on the TESTEN bit.
Table 77: Related Bit / Register In Chapter 3.27.1
IDT82P2282
Note:
* ID means Indirect Register in the Receive & Transmit Payload Control function blocks.
The PRBS Generator / Detector generates test pattern to either the
Three patterns are generated: 2
The selected pattern is generated once there is a transition from ‘0’
TESTING AND DIAGNOSTIC FACILITIES
PRBSMODE[1:0]
PRBS GENERATOR / DETECTOR
PRBSDIR
PATS[1:0]
TESTEN
Pattern Generator
SYNCV
SYNCE
SYNCI
BERE
TEST
RINV
TINV
BERI
INV
Bit
20
-1 pattern per O.150-4.5. They are selected by
11
-1 pattern per O.150, 2
TPLC / RPLC / PRGD Test Configuration
ID * - Signaling Trunk Conditioning Code
PRGD Status/Error Control
PRGD Interrupt Indication
PRGD Control
Register
15
-1 pat-
103
INV bit is set to ‘1’. Before the insertion, the generated pattern can be
inverted when the TINV bit is set.
3.27.1.2
tern detector starts to extract the data. The extracted data is used to re-
generate a desired pattern which is selected by the PATS[1:0] bits. The
extracted data is compared with the re-generated pattern. If the
extracted data coincides with the pattern, the pattern is synchronized
and it will be indicated by the SYNCV bit. In synchronization state, each
mismatched bit will generate a PRGD Bit Error event. This event is cap-
tured by the BERI bit and is forwarded to the Performance Monitor. An
interrupt reported on the INT pin will be enabled by the BERE bit if the
BERI bit is ‘1’. When there are more than 10-bit errors detected in the
fixed 48-bit window, the extracted data is out of synchronization and it
also will be indicated by the SYNCV bit. Any transition (from ‘1’ to ‘0’ or
from ‘0’ to ‘1’) on the SYNCV bit will set the SYNCI bit. An interrupt
reported on the INT pin will be enabled by the SYNCE bit if the SYNCI
bit is ‘1’.
inverted by setting the RINV bit.
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
A single bit error will be inserted to the generated pattern when the
When there is a transition from ‘0’ to ‘1’ on the TESTEN bit, the pat-
Before the data extracted to the pattern detector, the data can be
RPLC & TPLC ID * - 41~58 (for T1/J1) / 41~4F & 51~5F (for E1)
Pattern Detector
Address (Hex)
0C7, 1C7
071, 171
072, 172
073, 173
August 20, 2009