MT48H8M16LFB4-75:K Micron Technology Inc, MT48H8M16LFB4-75:K Datasheet - Page 78

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MT48H8M16LFB4-75:K

Manufacturer Part Number
MT48H8M16LFB4-75:K
Description
DRAM Chip Mobile SDRAM 128M-Bit 8Mx16 1.8V 54-Pin VFBGA Tray
Manufacturer
Micron Technology Inc
Type
Mobile SDRAMr
Series
-r
Datasheet

Specifications of MT48H8M16LFB4-75:K

Package
54VFBGA
Density
128 Mb
Address Bus Width
14 Bit
Operating Supply Voltage
1.8 V
Maximum Clock Rate
133 MHz
Maximum Random Access Time
8|5.4 ns
Operating Temperature
0 to 70 °C
Format - Memory
RAM
Memory Type
Mobile SDRAM
Memory Size
128M (8Mx16)
Speed
132MHz
Interface
Parallel
Voltage - Supply
1.7 V ~ 1.95 V
Package / Case
54-VFBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MT48H8M16LFB4-75:K
Manufacturer:
MICRON
Quantity:
4 000
Part Number:
MT48H8M16LFB4-75:K
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Part Number:
MT48H8M16LFB4-75:K TR
Manufacturer:
Micron Technology Inc
Quantity:
10 000
SELF REFRESH Operation
PDF: 09005aef832ff1ea
128mb_mobile_sdram_y35M.pdf - Rev. G 10/09 EN
The self refresh mode can be used to retain data in the device, even when the rest of the
system is powered down. When in self refresh mode, the device retains data without
external clocking. The SELF REFRESH command is initiated like an AUTO REFRESH
command, except CKE is disabled (LOW). After the SELF REFRESH command is regis-
tered, all the inputs to the device become “Don’t Care” with the exception of CKE,
which must remain LOW.
After self refresh mode is engaged, the device provides its own internal clocking, ena-
bling it to perform its own AUTO REFRESH cycles. The device must remain in self
refresh mode for a minimum period equal to
an indefinite period beyond that.
The procedure for exiting self refresh requires a sequence of commands. First, CLK
must be stable prior to CKE going back HIGH. (Stable clock is defined as a signal cycling
within timing constraints specified for the clock ball.) After CKE is HIGH, the device
must have NOP commands issued for a minimum of two clocks for
required for the completion of any internal refresh in progress.
Upon exiting the self refresh mode, AUTO REFRESH commands must be issued accord-
ing to the distributed refresh rate (
AUTO REFRESH utilize the row refresh counter.
128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM
78
t
REF/refresh row count) as both SELF REFRESH and
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
RAS and remains in self refresh mode for
SELF REFRESH Operation
©2008 Micron Technology, Inc. All rights reserved.
t
XSR because time is

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