MT48H8M16LFB4-75:K Micron Technology Inc, MT48H8M16LFB4-75:K Datasheet - Page 46

no-image

MT48H8M16LFB4-75:K

Manufacturer Part Number
MT48H8M16LFB4-75:K
Description
DRAM Chip Mobile SDRAM 128M-Bit 8Mx16 1.8V 54-Pin VFBGA Tray
Manufacturer
Micron Technology Inc
Type
Mobile SDRAMr
Series
-r
Datasheet

Specifications of MT48H8M16LFB4-75:K

Package
54VFBGA
Density
128 Mb
Address Bus Width
14 Bit
Operating Supply Voltage
1.8 V
Maximum Clock Rate
133 MHz
Maximum Random Access Time
8|5.4 ns
Operating Temperature
0 to 70 °C
Format - Memory
RAM
Memory Type
Mobile SDRAM
Memory Size
128M (8Mx16)
Speed
132MHz
Interface
Parallel
Voltage - Supply
1.7 V ~ 1.95 V
Package / Case
54-VFBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MT48H8M16LFB4-75:K
Manufacturer:
MICRON
Quantity:
4 000
Part Number:
MT48H8M16LFB4-75:K
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Part Number:
MT48H8M16LFB4-75:K TR
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Bank/Row Activation
Figure 16: Example: Meeting
PDF: 09005aef832ff1ea
128mb_mobile_sdram_y35M.pdf - Rev. G 10/09 EN
Command
Before any READ or WRITE commands can be issued to a bank within the SDRAM, a
row in that bank must be opened. This is accomplished via the ACTIVE command,
which selects both the bank and the row to be activated.
After a row is opened with the ACTIVE command, a READ or WRITE command can be
issued to that row, subject to the
the clock period and rounded up to the next whole number to determine the earliest
clock edge after the ACTIVE command on which a READ or WRITE command can be
entered. For example, a
results in 2.5 clocks, rounded to 3. This is reflected in Figure 16 (page 46), which cov-
ers any case where 2 <
other specification limits from time units to clock cycles.)
A subsequent ACTIVE command to a different row in the same bank can only be issued
after the previous active row has been precharged. The minimum time interval between
successive ACTIVE commands to the same bank is defined by
A subsequent ACTIVE command to another bank can be issued while the first bank is
being accessed, which results in a reduction of total row-access overhead. The mini-
mum time interval between successive ACTIVE commands to different banks is defined
by
t
RRD.
CLK
t
RCD (MIN) When 2 <
ACTIVE
T0
t CK
t
RCD (MIN)/
128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM
t
RCD specification of 20ns with a 125 MHz clock (8ns period)
NOP
t
RCD(MIN)
T1
46
t
RCD (MIN)/
t CK
t
RCD specification.
t
CK ≤ 3. (The same procedure is used to convert
NOP
Micron Technology, Inc. reserves the right to change products or specifications without notice.
T2
t
CK < 3
t CK
READ or
WRITE
t
RCD (MIN) should be divided by
Don’t Care
T3
Bank/Row Activation
©2008 Micron Technology, Inc. All rights reserved.
t
RC.

Related parts for MT48H8M16LFB4-75:K